#Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010
#install: C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A
#OS:  6.1
#Hostname: WIN-K2PJVCLULR9

#Implementation: synthesis

#Sat Oct 09 10:40:34 2010

$ Start of Compile
#Sat Oct 09 10:40:34 2010

Synopsys Verilog Compiler, version comp475rc, Build 060R, built Jan 15 2010
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

@I::"C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\proasic\smartfusion.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\COREI2C\6.0.104\rtl\vlog\core_obfuscated\corei2creal.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\COREI2C\6.0.104\rtl\vlog\core_obfuscated\corei2c.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\hdl\i2ctribuf.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\SmartFusionMSS\MSS\2.2.101\mss_comps.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\work\mycore\MSS_CCC_0\mycore_tmp_MSS_CCC_0_MSS_CCC.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\work\mycore\mycore.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vlog\core_obfuscated\Clock_gen.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vlog\core_obfuscated\Tx_async.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vlog\core_obfuscated\Rx_async.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vlog\core_obfuscated\fifo_256x8_pa3.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vlog\core_obfuscated\CoreUART.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vlog\core_obfuscated\CoreUARTapb.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core_obfuscated\spi_master.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core_obfuscated\spi_slave.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core_obfuscated\corespi_sfr.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core_obfuscated\corespi.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v"
@I::"Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\work\mytop\mytop.v"
Verilog syntax check successful!
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\COREI2C\6.0.104\rtl\vlog\core_obfuscated\corei2creal.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\COREI2C\6.0.104\rtl\vlog\core_obfuscated\corei2c.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\SmartFusionMSS\MSS\2.2.101\mss_comps.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\work\mycore\MSS_CCC_0\mycore_tmp_MSS_CCC_0_MSS_CCC.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\work\mycore\mycore.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\hdl\i2ctribuf.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vlog\core_obfuscated\Clock_gen.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vlog\core_obfuscated\Tx_async.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vlog\core_obfuscated\Rx_async.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vlog\core_obfuscated\fifo_256x8_pa3.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vlog\core_obfuscated\CoreUART.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreUARTapb\4.1.113\rtl\vlog\core_obfuscated\CoreUARTapb.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core_obfuscated\spi_master.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core_obfuscated\spi_slave.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core_obfuscated\corespi_sfr.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core_obfuscated\corespi.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v changed - recompiling
File Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\component\work\mytop\mytop.v changed - recompiling
Selecting top level module mytop
@W:CG775 : coreapb3.v(13) | Found Component CoreAPB3 in library COREAPB3_LIB
@N:CG364 : coreapb3_muxptob3.v(13) | Synthesizing module CAPB3O

@N:CG364 : coreapb3.v(13) | Synthesizing module CoreAPB3

	APB_DWIDTH=6'b100000
	RANGESIZE=21'b000000000001000000000
	IADDR_ENABLE=1'b0
	APBSLOT0ENABLE=1'b1
	APBSLOT1ENABLE=1'b1
	APBSLOT2ENABLE=1'b1
	APBSLOT3ENABLE=1'b1
	APBSLOT4ENABLE=1'b0
	APBSLOT5ENABLE=1'b0
	APBSLOT6ENABLE=1'b0
	APBSLOT7ENABLE=1'b0
	APBSLOT8ENABLE=1'b0
	APBSLOT9ENABLE=1'b0
	APBSLOT10ENABLE=1'b0
	APBSLOT11ENABLE=1'b0
	APBSLOT12ENABLE=1'b0
	APBSLOT13ENABLE=1'b0
	APBSLOT14ENABLE=1'b0
	APBSLOT15ENABLE=1'b0
	CAPB3O1I=32'b00000000000000000000000000001001
	CAPB3I1I=32'b00000000000000000000000000001001
	CAPB3l1I=9'b000001100
	CAPB3OOl=9'b000001000
	CAPB3IOl=9'b000000100
	CAPB3lOl=9'b000000000
	CAPB3OIl=9'b000000100
	CAPB3IIl=9'b000000000
	CAPB3lIl=9'b000000000
	CAPB3Oll=16'b0000000000000001
	CAPB3Ill=16'b0000000000000010
	CAPB3lll=16'b0000000000000100
	CAPB3O0l=16'b0000000000001000
	CAPB3I0l=16'b0000000000000000
	CAPB3l0l=16'b0000000000000000
	CAPB3O1l=16'b0000000000000000
	CAPB3I1l=16'b0000000000000000
	CAPB3l1l=16'b0000000000000000
	CAPB3OO0=16'b0000000000000000
	CAPB3IO0=16'b0000000000000000
	CAPB3lO0=16'b0000000000000000
	CAPB3OI0=16'b0000000000000000
	CAPB3II0=16'b0000000000000000
	CAPB3lI0=16'b0000000000000000
	CAPB3Ol0=16'b0000000000000000
   Generated name = CoreAPB3_Z1

@N:CG364 : smartfusion.v(1814) | Synthesizing module VCC

@N:CG364 : corei2c.v(7) | Synthesizing module COREI2C

	FAMILY=32'b00000000000000000000000000010001
	OPERATING_MODE=32'b00000000000000000000000000000001
	BAUD_RATE_FIXED=32'b00000000000000000000000000000000
	BAUD_RATE_VALUE=32'b00000000000000000000000000000000
	BCLK_ENABLED=32'b00000000000000000000000000000000
	GLITCHREG_NUM=32'b00000000000000000000000000000011
	SMB_EN=32'b00000000000000000000000000000000
	IPMI_EN=32'b00000000000000000000000000000000
	FREQUENCY=32'b00000000000000000000000000011110
	FIXED_SLAVE0_ADDR_EN=32'b00000000000000000000000000000000
	FIXED_SLAVE0_ADDR_VALUE=32'b00000000000000000000000000000000
	ADD_SLAVE1_ADDRESS_EN=32'b00000000000000000000000000000000
	FIXED_SLAVE1_ADDR_EN=32'b00000000000000000000000000000000
	FIXED_SLAVE1_ADDR_VALUE=32'b00000000000000000000000000000000
	I2C_NUM=32'b00000000000000000000000000000001
	CI2CII=5'b01100
	CI2ClI=8'b00000000
	CI2COl=5'b11100
	CI2CIl=8'b00000000
   Generated name = COREI2C_Z2

@N:CG364 : corei2creal.v(7) | Synthesizing module COREI2CREAL

	FAMILY=32'b00000000000000000000000000010001
	OPERATING_MODE=32'b00000000000000000000000000000001
	BAUD_RATE_FIXED=32'b00000000000000000000000000000000
	BAUD_RATE_VALUE=32'b00000000000000000000000000000000
	BCLK_ENABLED=32'b00000000000000000000000000000000
	GLITCHREG_NUM=32'b00000000000000000000000000000011
	SMB_EN=32'b00000000000000000000000000000000
	IPMI_EN=32'b00000000000000000000000000000000
	FREQUENCY=32'b00000000000000000000000000011110
	FIXED_SLAVE0_ADDR_EN=32'b00000000000000000000000000000000
	FIXED_SLAVE0_ADDR_VALUE=32'b00000000000000000000000000000000
	ADD_SLAVE1_ADDRESS_EN=32'b00000000000000000000000000000000
	FIXED_SLAVE1_ADDR_EN=32'b00000000000000000000000000000000
	FIXED_SLAVE1_ADDR_VALUE=32'b00000000000000000000000000000000
	CI2CI0l=32'b00000000000000000000000000000100
	CI2Cl0l=4'b0101
	CI2CO1l=1'b0
	CI2CI1l=1'b1
	CI2Cl1l=5'b00000
	CI2COO0=8'b00000000
	CI2CIO0=5'b00100
	CI2ClO0=8'b11111000
	CI2COI0=5'b01000
	CI2CII0=8'b00000000
	CI2ClI0=5'b10000
	CI2COl0=8'b01x1x000
	CI2CII=5'b01100
	CI2ClI=8'b00000000
	CI2COl=5'b11100
	CI2CIl=8'b00000000
	CI2CIl0=5'b00000
	CI2Cll0=5'b00001
	CI2CO00=5'b00010
	CI2CI00=5'b00011
	CI2Cl00=5'b00100
	CI2CO10=5'b00101
	CI2CI10=5'b00110
	CI2Cl10=5'b00111
	CI2COO1=5'b01000
	CI2CIO1=5'b01001
	CI2ClO1=5'b01010
	CI2COI1=5'b01011
	CI2CII1=5'b01100
	CI2ClI1=5'b01101
	CI2COl1=5'b01110
	CI2CIl1=5'b01111
	CI2Cll1=5'b10000
	CI2CO01=5'b10001
	CI2CI01=5'b10010
	CI2Cl01=5'b10011
	CI2CO11=5'b10100
	CI2CI11=5'b10101
	CI2Cl11=5'b10110
	CI2COOOI=5'b10111
	CI2CIOOI=5'b11000
	CI2ClOOI=5'b11001
	CI2COIOI=5'b11010
	CI2CIIOI=5'b11011
	CI2ClIOI=5'b11100
	CI2COlOI=3'b000
	CI2CIlOI=3'b001
	CI2CllOI=3'b010
	CI2CO0OI=3'b011
	CI2CI0OI=3'b100
	CI2Cl0OI=3'b101
	CI2CO1OI=3'b110
	CI2CI1OI=3'b000
	CI2Cl1OI=3'b001
	CI2COOII=3'b010
	CI2CIOII=3'b011
	CI2ClOII=3'b100
	CI2COIII=3'b101
	CI2CIIII=3'b110
	CI2ClIII=3'b111
	CI2COlII=3'b000
	CI2CIlII=3'b001
	CI2CllII=3'b010
	CI2CO0II=3'b011
	CI2CI0II=3'b100
	CI2Cl0II=3'b101
	CI2CO1II=3'b110
	CI2CI1II=32'b00000000000000000000000000001000
	CI2Cl1II=32'b00000000000000000000000000000111
   Generated name = COREI2CREAL_Z3

@W:CG133 : corei2creal.v(1028) | No assignment to CI2COl0I
@W:CG133 : corei2creal.v(1031) | No assignment to CI2CIl0I
@W:CG133 : corei2creal.v(1037) | No assignment to CI2CO00I
@W:CG133 : corei2creal.v(1043) | No assignment to CI2Cl00I
@W:CG133 : corei2creal.v(1046) | No assignment to CI2CO10I
@W:CG133 : corei2creal.v(1049) | No assignment to CI2CI10I
@W:CG133 : corei2creal.v(1096) | No assignment to CI2CI11I
@W:CG133 : corei2creal.v(1098) | No assignment to CI2Cl11I
@W:CG133 : corei2creal.v(1101) | No assignment to CI2COOOl
@W:CG133 : corei2creal.v(1103) | No assignment to CI2CIOOl
@W:CL169 : corei2creal.v(8683) | Pruning Register CI2CIllI[3:0] 

@W:CL169 : corei2creal.v(8567) | Pruning Register CI2CIIlI[6:0] 

@W:CL169 : corei2creal.v(8436) | Pruning Register CI2CIOlI[7:0] 

@W:CL169 : corei2creal.v(7873) | Pruning Register CI2CIOll 

@W:CL169 : corei2creal.v(3353) | Pruning Register CI2CIl1I 

@W:CL169 : corei2creal.v(3353) | Pruning Register CI2COl1I 

@W:CL169 : corei2creal.v(3353) | Pruning Register CI2Cll1I 

@W:CL169 : corei2creal.v(6954) | Pruning Register CI2CO01I 

@W:CL190 : corei2creal.v(6954) | Optimizing register bit CI2CI01I to a constant 1
@W:CL169 : corei2creal.v(6954) | Pruning Register CI2CI01I 

@W:CG133 : corei2c.v(407) | No assignment to CI2CI1
@W:CL169 : corei2c.v(537) | Pruning Register CI2CI0 

@W:CL169 : corei2c.v(537) | Pruning Register CI2Cl0 

@W:CL169 : corei2c.v(453) | Pruning Register CI2CO0[12:0] 

@N:CG364 : corei2c.v(7) | Synthesizing module COREI2C

	FAMILY=32'b00000000000000000000000000010001
	OPERATING_MODE=32'b00000000000000000000000000000000
	BAUD_RATE_FIXED=32'b00000000000000000000000000000000
	BAUD_RATE_VALUE=32'b00000000000000000000000000000000
	BCLK_ENABLED=32'b00000000000000000000000000000000
	GLITCHREG_NUM=32'b00000000000000000000000000000011
	SMB_EN=32'b00000000000000000000000000000000
	IPMI_EN=32'b00000000000000000000000000000000
	FREQUENCY=32'b00000000000000000000000000011110
	FIXED_SLAVE0_ADDR_EN=32'b00000000000000000000000000000000
	FIXED_SLAVE0_ADDR_VALUE=32'b00000000000000000000000000000000
	ADD_SLAVE1_ADDRESS_EN=32'b00000000000000000000000000000000
	FIXED_SLAVE1_ADDR_EN=32'b00000000000000000000000000000000
	FIXED_SLAVE1_ADDR_VALUE=32'b00000000000000000000000000000000
	I2C_NUM=32'b00000000000000000000000000000001
	CI2CII=5'b01100
	CI2ClI=8'b00000000
	CI2COl=5'b11100
	CI2CIl=8'b00000000
   Generated name = COREI2C_Z4

@N:CG364 : corei2creal.v(7) | Synthesizing module COREI2CREAL

	FAMILY=32'b00000000000000000000000000010001
	OPERATING_MODE=32'b00000000000000000000000000000000
	BAUD_RATE_FIXED=32'b00000000000000000000000000000000
	BAUD_RATE_VALUE=32'b00000000000000000000000000000000
	BCLK_ENABLED=32'b00000000000000000000000000000000
	GLITCHREG_NUM=32'b00000000000000000000000000000011
	SMB_EN=32'b00000000000000000000000000000000
	IPMI_EN=32'b00000000000000000000000000000000
	FREQUENCY=32'b00000000000000000000000000011110
	FIXED_SLAVE0_ADDR_EN=32'b00000000000000000000000000000000
	FIXED_SLAVE0_ADDR_VALUE=32'b00000000000000000000000000000000
	ADD_SLAVE1_ADDRESS_EN=32'b00000000000000000000000000000000
	FIXED_SLAVE1_ADDR_EN=32'b00000000000000000000000000000000
	FIXED_SLAVE1_ADDR_VALUE=32'b00000000000000000000000000000000
	CI2CI0l=32'b00000000000000000000000000000100
	CI2Cl0l=4'b0101
	CI2CO1l=1'b0
	CI2CI1l=1'b0
	CI2Cl1l=5'b00000
	CI2COO0=8'b00000000
	CI2CIO0=5'b00100
	CI2ClO0=8'b11111000
	CI2COI0=5'b01000
	CI2CII0=8'b00000000
	CI2ClI0=5'b10000
	CI2COl0=8'b01x1x000
	CI2CII=5'b01100
	CI2ClI=8'b00000000
	CI2COl=5'b11100
	CI2CIl=8'b00000000
	CI2CIl0=5'b00000
	CI2Cll0=5'b00001
	CI2CO00=5'b00010
	CI2CI00=5'b00011
	CI2Cl00=5'b00100
	CI2CO10=5'b00101
	CI2CI10=5'b00110
	CI2Cl10=5'b00111
	CI2COO1=5'b01000
	CI2CIO1=5'b01001
	CI2ClO1=5'b01010
	CI2COI1=5'b01011
	CI2CII1=5'b01100
	CI2ClI1=5'b01101
	CI2COl1=5'b01110
	CI2CIl1=5'b01111
	CI2Cll1=5'b10000
	CI2CO01=5'b10001
	CI2CI01=5'b10010
	CI2Cl01=5'b10011
	CI2CO11=5'b10100
	CI2CI11=5'b10101
	CI2Cl11=5'b10110
	CI2COOOI=5'b10111
	CI2CIOOI=5'b11000
	CI2ClOOI=5'b11001
	CI2COIOI=5'b11010
	CI2CIIOI=5'b11011
	CI2ClIOI=5'b11100
	CI2COlOI=3'b000
	CI2CIlOI=3'b001
	CI2CllOI=3'b010
	CI2CO0OI=3'b011
	CI2CI0OI=3'b100
	CI2Cl0OI=3'b101
	CI2CO1OI=3'b110
	CI2CI1OI=3'b000
	CI2Cl1OI=3'b001
	CI2COOII=3'b010
	CI2CIOII=3'b011
	CI2ClOII=3'b100
	CI2COIII=3'b101
	CI2CIIII=3'b110
	CI2ClIII=3'b111
	CI2COlII=3'b000
	CI2CIlII=3'b001
	CI2CllII=3'b010
	CI2CO0II=3'b011
	CI2CI0II=3'b100
	CI2Cl0II=3'b101
	CI2CO1II=3'b110
	CI2CI1II=32'b00000000000000000000000000001000
	CI2Cl1II=32'b00000000000000000000000000000111
   Generated name = COREI2CREAL_Z5

@W:CG133 : corei2creal.v(1028) | No assignment to CI2COl0I
@W:CG133 : corei2creal.v(1031) | No assignment to CI2CIl0I
@W:CG133 : corei2creal.v(1037) | No assignment to CI2CO00I
@W:CG133 : corei2creal.v(1043) | No assignment to CI2Cl00I
@W:CG133 : corei2creal.v(1046) | No assignment to CI2CO10I
@W:CG133 : corei2creal.v(1049) | No assignment to CI2CI10I
@W:CG133 : corei2creal.v(1096) | No assignment to CI2CI11I
@W:CG133 : corei2creal.v(1098) | No assignment to CI2Cl11I
@W:CG133 : corei2creal.v(1101) | No assignment to CI2COOOl
@W:CG133 : corei2creal.v(1103) | No assignment to CI2CIOOl
@W:CL169 : corei2creal.v(8683) | Pruning Register CI2CIllI[3:0] 

@W:CL169 : corei2creal.v(8567) | Pruning Register CI2CIIlI[6:0] 

@W:CL169 : corei2creal.v(8436) | Pruning Register CI2CIOlI[7:0] 

@W:CL169 : corei2creal.v(3353) | Pruning Register CI2CIl1I 

@W:CL169 : corei2creal.v(3353) | Pruning Register CI2COl1I 

@W:CL169 : corei2creal.v(3353) | Pruning Register CI2Cll1I 

@W:CL169 : corei2creal.v(6954) | Pruning Register CI2CO01I 

@W:CL190 : corei2creal.v(6954) | Optimizing register bit CI2CI01I to a constant 1
@W:CL169 : corei2creal.v(6954) | Pruning Register CI2CI01I 

@W:CG133 : corei2c.v(407) | No assignment to CI2CI1
@W:CL169 : corei2c.v(537) | Pruning Register CI2CI0 

@W:CL169 : corei2c.v(537) | Pruning Register CI2Cl0 

@W:CL169 : corei2c.v(453) | Pruning Register CI2CO0[12:0] 

@N:CG364 : i2ctribuf.v(2) | Synthesizing module i2ctribuf

@N:CG364 : smartfusion.v(1133) | Synthesizing module GND

@N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS

@N:CG364 : mss_comps.v(37) | Synthesizing module OUTBUF_MSS

@N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC

@N:CG364 : mss_comps.v(1) | Synthesizing module MSS_XTLOSC

@N:CG364 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module mycore_tmp_MSS_CCC_0_MSS_CCC

@N:CG364 : mss_comps.v(680) | Synthesizing module MSS_APB

@N:CG364 : mss_comps.v(145) | Synthesizing module MSSINT

@N:CG364 : mycore.v(5) | Synthesizing module mycore

@N:CG364 : Clock_gen.v(26) | Synthesizing module CUARTII

@N:CG364 : Tx_async.v(10) | Synthesizing module CUARTO10

	TX_FIFO=32'b00000000000000000000000000000000
	CUARTl1Il=32'b00000000000000000000000000000000
	CUARTOOll=32'b00000000000000000000000000000001
	CUARTIOll=32'b00000000000000000000000000000010
	CUARTlOll=32'b00000000000000000000000000000011
	CUARTOIll=32'b00000000000000000000000000000100
	CUARTIIll=32'b00000000000000000000000000000101
	CUARTlIll=32'b00000000000000000000000000000110
   Generated name = CUARTO10_0s_0s_1s_2s_3s_4s_5s_6s

@N:CG179 : Tx_async.v(825) | Removing redundant assignment
@W:CL190 : Tx_async.v(255) | Optimizing register bit CUARTl0ll to a constant 1
@W:CL169 : Tx_async.v(255) | Pruning Register CUARTl0ll 

@N:CG364 : Rx_async.v(10) | Synthesizing module CUARTOl1

	RX_FIFO=32'b00000000000000000000000000000000
	RX_LEGACY_MODE=32'b00000000000000000000000000000000
	CUARTlOIl=32'b00000000000000000000000000000000
	CUARTOIIl=32'b00000000000000000000000000000001
	CUARTIIIl=32'b00000000000000000000000000000010
   Generated name = CUARTOl1_0s_0s_0s_1s_2s

@N:CG179 : Rx_async.v(655) | Removing redundant assignment
@N:CL177 : Rx_async.v(1415) | Sharing sequential element CUARTO0l.
@N:CG364 : CoreUART.v(10) | Synthesizing module COREUART

	TX_FIFO=32'b00000000000000000000000000000000
	RX_FIFO=32'b00000000000000000000000000000000
	RX_LEGACY_MODE=32'b00000000000000000000000000000000
	FAMILY=32'b00000000000000000000000000001111
   Generated name = COREUART_0s_0s_0s_15s

@N:CG179 : CoreUART.v(1190) | Removing redundant assignment
@W:CG360 : CoreUART.v(215) | No assignment to wire CUARTO0I

@W:CG360 : CoreUART.v(223) | No assignment to wire CUARTI0I

@W:CG360 : CoreUART.v(253) | No assignment to wire CUARTOOl

@W:CG360 : CoreUART.v(256) | No assignment to wire CUARTIOl

@W:CG360 : CoreUART.v(268) | No assignment to wire CUARTlIl

@W:CG360 : CoreUART.v(271) | No assignment to wire CUARTOll

@W:CG133 : CoreUART.v(301) | No assignment to CUARTIO0
@W:CL169 : CoreUART.v(1124) | Pruning Register CUARTll0 

@W:CL169 : CoreUART.v(1043) | Pruning Register CUARTlO0 

@W:CL169 : CoreUART.v(1043) | Pruning Register CUARTOI0 

@W:CL169 : CoreUART.v(994) | Pruning Register CUARTO1I[7:0] 

@W:CL169 : CoreUART.v(876) | Pruning Register CUARTII0[1:0] 

@W:CL169 : CoreUART.v(832) | Pruning Register CUARTl1l 

@W:CL169 : CoreUART.v(832) | Pruning Register CUARTI1l 

@W:CL169 : CoreUART.v(788) | Pruning Register CUARTl0l 

@W:CL169 : CoreUART.v(788) | Pruning Register CUARTI0l 

@W:CL169 : CoreUART.v(337) | Pruning Register CUARTOIl 

@N:CG364 : CoreUARTapb.v(10) | Synthesizing module CoreUARTapb

	FAMILY=32'b00000000000000000000000000001111
	TX_FIFO=32'b00000000000000000000000000000000
	RX_FIFO=32'b00000000000000000000000000000000
	BAUD_VALUE=32'b00000000000000000000000000000001
	FIXEDMODE=32'b00000000000000000000000000000000
	PRG_BIT8=32'b00000000000000000000000000000000
	PRG_PARITY=32'b00000000000000000000000000000000
	RX_LEGACY_MODE=32'b00000000000000000000000000000000
   Generated name = CoreUARTapb_15s_0s_0s_1s_0s_0s_0s_0s

@N:CG179 : CoreUARTapb.v(609) | Removing redundant assignment
@N:CG179 : CoreUARTapb.v(685) | Removing redundant assignment
@N:CG364 : corespi_sfr.v(5) | Synthesizing module CSPIlI

	USE_MASTER=32'b00000000000000000000000000000001
	USE_SLAVE=32'b00000000000000000000000000000000
   Generated name = CSPIlI_1s_0s

@N:CG364 : spi_master.v(5) | Synthesizing module spi_master

@W:CL118 : spi_master.v(731) | Latch generated from always block for signal CSPIll0[3:0], probably caused by a missing assignment in an if or case stmt
@N:CG364 : corespi.v(4) | Synthesizing module CORESPI

	FAMILY=32'b00000000000000000000000000001111
	USE_MASTER=32'b00000000000000000000000000000001
	USE_SLAVE=32'b00000000000000000000000000000000
   Generated name = CORESPI_15s_1s_0s

@N:CG364 : mytop.v(5) | Synthesizing module mytop

@W:CL246 : corespi.v(70) | Input port bits 1 to 0 of PADDR[3:0] are unused

@W:CL159 : corespi_sfr.v(84) | Input s_sck is unused
@W:CL159 : corespi_sfr.v(90) | Input s_mosi is unused
@W:CL159 : corespi_sfr.v(93) | Input s_ss is unused
@W:CL246 : CoreUARTapb.v(93) | Input port bits 1 to 0 of PADDR[4:0] are unused

@W:CL156 : CoreUART.v(1271) | *Input CUARTO0I[7:0] to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W:CL156 : CoreUART.v(1271) | *Input CUARTOOl to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W:CL156 : CoreUART.v(1271) | *Input CUARTlIl to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@N:CL201 : Rx_async.v(724) | Trying to extract state machine for register CUARTII0
Extracted state machine for register CUARTII0
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W:CL190 : Tx_async.v(528) | Optimizing register bit CUARTO1ll to a constant 1
@W:CL190 : Tx_async.v(528) | Optimizing register bit CUARTIIl to a constant 1
@W:CL169 : Tx_async.v(528) | Pruning Register CUARTIIl 

@W:CL169 : Tx_async.v(528) | Pruning Register CUARTO1ll 

@N:CL201 : Tx_async.v(255) | Trying to extract state machine for register CUARTOlll
Extracted state machine for register CUARTOlll
State machine has 6 reachable states with original encodings of:
   00000000000000000000000000000000
   00000000000000000000000000000001
   00000000000000000000000000000010
   00000000000000000000000000000011
   00000000000000000000000000000100
   00000000000000000000000000000101
@W:CL159 : Tx_async.v(72) | Input CUARTO0I is unused
@W:CL159 : Tx_async.v(75) | Input CUARTl10 is unused
@W:CL159 : Tx_async.v(78) | Input CUARTOO1 is unused
@W:CL157 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible 
@W:CL157 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible 
@W:CL157 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible 
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused
@W:CL159 : mycore_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused
@N:CL201 : corei2creal.v(8255) | Trying to extract state machine for register CI2CI0lI
Extracted state machine for register CI2CI0lI
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@N:CL201 : corei2creal.v(7679) | Trying to extract state machine for register CI2Cl1lI
Extracted state machine for register CI2Cl1lI
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@N:CL201 : corei2creal.v(5507) | Trying to extract state machine for register CI2CO1lI
Extracted state machine for register CI2CO1lI
State machine has 8 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
   111
@W:CL159 : corei2creal.v(88) | Input pulse_215us is unused
@W:CL159 : corei2creal.v(104) | Input seradr1apb0 is unused
@W:CL159 : corei2creal.v(149) | Input SMBALERT_NI is unused
@W:CL159 : corei2creal.v(155) | Input SMBSUS_NI is unused
@W:CL159 : corei2c.v(97) | Input BCLK is unused
@N:CL201 : corei2creal.v(8255) | Trying to extract state machine for register CI2CI0lI
@N:CL201 : corei2creal.v(7679) | Trying to extract state machine for register CI2Cl1lI
Extracted state machine for register CI2Cl1lI
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@N:CL201 : corei2creal.v(5507) | Trying to extract state machine for register CI2CO1lI
Extracted state machine for register CI2CO1lI
State machine has 6 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
@W:CL190 : corei2creal.v(8255) | Optimizing register bit CI2CI0lI[0] to a constant 0
@W:CL260 : corei2creal.v(8255) | Pruning Register bit 0 of CI2CI0lI[2:0] 

@W:CL190 : corei2creal.v(7812) | Optimizing register bit CI2COOll to a constant 0
@W:CL169 : corei2creal.v(7812) | Pruning Register CI2COOll 

@W:CL159 : corei2creal.v(88) | Input pulse_215us is unused
@W:CL159 : corei2creal.v(104) | Input seradr1apb0 is unused
@W:CL159 : corei2creal.v(149) | Input SMBALERT_NI is unused
@W:CL159 : corei2creal.v(155) | Input SMBSUS_NI is unused
@W:CL159 : corei2c.v(97) | Input BCLK is unused
@W:CL246 : coreapb3.v(217) | Input port bits 23 to 13 of PADDR[23:0] are unused

@W:CL159 : coreapb3.v(208) | Input PRESETN is unused
@W:CL159 : coreapb3.v(210) | Input PCLK is unused
@W:CL159 : coreapb3.v(377) | Input PRDATAS4 is unused
@W:CL159 : coreapb3.v(384) | Input PRDATAS5 is unused
@W:CL159 : coreapb3.v(391) | Input PRDATAS6 is unused
@W:CL159 : coreapb3.v(398) | Input PRDATAS7 is unused
@W:CL159 : coreapb3.v(405) | Input PRDATAS8 is unused
@W:CL159 : coreapb3.v(412) | Input PRDATAS9 is unused
@W:CL159 : coreapb3.v(419) | Input PRDATAS10 is unused
@W:CL159 : coreapb3.v(426) | Input PRDATAS11 is unused
@W:CL159 : coreapb3.v(433) | Input PRDATAS12 is unused
@W:CL159 : coreapb3.v(440) | Input PRDATAS13 is unused
@W:CL159 : coreapb3.v(447) | Input PRDATAS14 is unused
@W:CL159 : coreapb3.v(454) | Input PRDATAS15 is unused
@W:CL159 : coreapb3.v(464) | Input PREADYS4 is unused
@W:CL159 : coreapb3.v(466) | Input PREADYS5 is unused
@W:CL159 : coreapb3.v(468) | Input PREADYS6 is unused
@W:CL159 : coreapb3.v(470) | Input PREADYS7 is unused
@W:CL159 : coreapb3.v(472) | Input PREADYS8 is unused
@W:CL159 : coreapb3.v(474) | Input PREADYS9 is unused
@W:CL159 : coreapb3.v(476) | Input PREADYS10 is unused
@W:CL159 : coreapb3.v(478) | Input PREADYS11 is unused
@W:CL159 : coreapb3.v(480) | Input PREADYS12 is unused
@W:CL159 : coreapb3.v(482) | Input PREADYS13 is unused
@W:CL159 : coreapb3.v(484) | Input PREADYS14 is unused
@W:CL159 : coreapb3.v(486) | Input PREADYS15 is unused
@W:CL159 : coreapb3.v(496) | Input PSLVERRS4 is unused
@W:CL159 : coreapb3.v(498) | Input PSLVERRS5 is unused
@W:CL159 : coreapb3.v(500) | Input PSLVERRS6 is unused
@W:CL159 : coreapb3.v(502) | Input PSLVERRS7 is unused
@W:CL159 : coreapb3.v(504) | Input PSLVERRS8 is unused
@W:CL159 : coreapb3.v(506) | Input PSLVERRS9 is unused
@W:CL159 : coreapb3.v(508) | Input PSLVERRS10 is unused
@W:CL159 : coreapb3.v(510) | Input PSLVERRS11 is unused
@W:CL159 : coreapb3.v(512) | Input PSLVERRS12 is unused
@W:CL159 : coreapb3.v(514) | Input PSLVERRS13 is unused
@W:CL159 : coreapb3.v(516) | Input PSLVERRS14 is unused
@W:CL159 : coreapb3.v(518) | Input PSLVERRS15 is unused
@END
Process took 0h:00m:04s realtime, 0h:00m:03s cputime
# Sat Oct 09 10:40:39 2010

###########################################################]
Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
Product Version D-2009.12A
@N:MF249 :  | Running in 32-bit mode. 
@N:MF258 :  | Gated clock conversion disabled  

@W:MO111 : mycore_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module mycore_tmp_MSS_CCC_0_MSS_CCC) 
@W:MO111 : mycore_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module mycore_tmp_MSS_CCC_0_MSS_CCC) 
@W:MO111 : mycore_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module mycore_tmp_MSS_CCC_0_MSS_CCC) 
Automatic dissolve at startup in view:COREAPB3_LIB.CoreAPB3_Z1(verilog) of CAPB3llOI(CAPB3O)
Automatic dissolve at startup in view:work.mycore(verilog) of MSS_CCC_0(mycore_tmp_MSS_CCC_0_MSS_CCC)
Automatic dissolve at startup in view:work.mytop(verilog) of i2ctribuf_0(i2ctribuf)
Automatic dissolve at startup in view:work.mytop(verilog) of mycore_0(mycore)
Automatic dissolve at startup in view:work.mytop(verilog) of i2ctribuf_1(i2ctribuf)
Automatic dissolve at startup in view:work.mytop(verilog) of COREI2C_0(COREI2C_Z4)
Automatic dissolve at startup in view:work.mytop(verilog) of COREI2C_1(COREI2C_Z2)
Automatic dissolve at startup in view:work.mytop(verilog) of CoreAPB3_0(CoreAPB3_Z1)

Available hyper_sources - for debug and ip models
	None Found

Finished RTL optimizations (Time elapsed 0h:00m:03s; Memory used current: 57MB peak: 59MB)

@N: : corei2creal.v(4507) | Found counter in view:work.COREI2CREAL_Z3(verilog) inst CI2Cl1Ol[3:0]
@N: : corei2creal.v(4132) | Found counter in view:work.COREI2CREAL_Z3(verilog) inst CI2CI0Il[3:0]
@N: : corei2creal.v(4944) | Found counter in view:work.COREI2CREAL_Z3(verilog) inst CI2CIOIl[3:0]
@N:MO106 : corei2creal.v(2544) | Found ROM, 'CI2ClIll\.CI2ClI0I_2[4:0]', 28 words by 5 bits 
Encoding state machine work.COREI2CREAL_Z3(verilog)-CI2CO1lI[5:0]
original code -> new code
   000 -> 000001
   001 -> 000010
   010 -> 000100
   011 -> 001000
   100 -> 010000
   101 -> 100000
Encoding state machine work.COREI2CREAL_Z3(verilog)-CI2Cl1lI[6:0]
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
@W:MO161 : corei2creal.v(8255) | Register bit CI2CI0lI[2] is always 0, optimizing ...
@W:MO161 : corei2creal.v(8255) | Register bit CI2CI0lI[1] is always 0, optimizing ...
@N:BN116 : corei2creal.v(7727) | Removing sequential instance CI2Cl0Il of view:PrimLib.dffs(prim) because there are no references to its outputs 
@N:BN116 : corei2creal.v(5150) | Removing sequential instance CI2COIIl of view:PrimLib.dffs(prim) because there are no references to its outputs 
@N:BN116 : corei2creal.v(4944) | Removing sequential instance CI2CIOIl[3] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corei2creal.v(4944) | Removing sequential instance CI2CIOIl[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corei2creal.v(4944) | Removing sequential instance CI2CIOIl[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corei2creal.v(4944) | Removing sequential instance CI2CIOIl[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corei2creal.v(4507) | Removing sequential instance CI2Cl1Ol[3] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corei2creal.v(4507) | Removing sequential instance CI2Cl1Ol[2] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corei2creal.v(4507) | Removing sequential instance CI2Cl1Ol[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corei2creal.v(4507) | Removing sequential instance CI2Cl1Ol[0] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corei2creal.v(4507) | Removing sequential instance CI2COOIl of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corei2creal.v(4944) | Removing sequential instance CI2ClOIl of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corei2creal.v(5150) | Removing sequential instance CI2CIIIl of view:PrimLib.dffs(prim) because there are no references to its outputs 
@N: : corei2creal.v(4507) | Found counter in view:work.COREI2CREAL_Z5(verilog) inst CI2Cl1Ol[3:0]
@N: : corei2creal.v(4944) | Found counter in view:work.COREI2CREAL_Z5(verilog) inst CI2CIOIl[3:0]
@N: : corei2creal.v(4132) | Found counter in view:work.COREI2CREAL_Z5(verilog) inst CI2CI0Il[3:0]
@N:MO106 : corei2creal.v(2544) | Found ROM, 'CI2ClIll\.CI2ClI0I_6[4:0]', 28 words by 5 bits 
Encoding state machine work.COREI2CREAL_Z5(verilog)-CI2CO1lI[7:0]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
Encoding state machine work.COREI2CREAL_Z5(verilog)-CI2CI0lI[6:0]
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
Encoding state machine work.COREI2CREAL_Z5(verilog)-CI2Cl1lI[6:0]
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
@N: : clock_gen.v(87) | Found counter in view:work.CUARTII(verilog) inst CUARTI0[12:0]
@N: : clock_gen.v(162) | Found counter in view:work.CUARTII(verilog) inst CUARTI1[3:0]
@N: : tx_async.v(599) | Found counter in view:work.CUARTO10_0s_0s_1s_2s_3s_4s_5s_6s(verilog) inst CUARTO0ll[3:0]
Encoding state machine work.CUARTO10_0s_0s_1s_2s_3s_4s_5s_6s(verilog)-CUARTOlll[5:0]
original code -> new code
   00000000000000000000000000000000 -> 000001
   00000000000000000000000000000001 -> 000010
   00000000000000000000000000000010 -> 000100
   00000000000000000000000000000011 -> 001000
   00000000000000000000000000000100 -> 010000
   00000000000000000000000000000101 -> 100000
@N: : rx_async.v(968) | Found counter in view:work.CUARTOl1_0s_0s_0s_1s_2s(verilog) inst CUARTO0Ol[3:0]
@N: : rx_async.v(423) | Found counter in view:work.CUARTOl1_0s_0s_0s_1s_2s(verilog) inst CUARTlIOl[3:0]
Encoding state machine work.CUARTOl1_0s_0s_0s_1s_2s(verilog)-CUARTII0[2:0]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N: : spi_master.v(294) | Found counter in view:work.spi_master(verilog) inst CSPIOO1[7:0]
@N:MO106 : spi_master.v(731) | Found ROM, 'CSPIll1', 11 words by 1 bits 
Automatic dissolve during optimization of view:work.CoreUARTapb_15s_0s_0s_1s_0s_0s_0s_0s(verilog) of CUARTO1II(COREUART_0s_0s_0s_15s)
Automatic dissolve during optimization of view:work.mytop(verilog) of CORESPI_0(CORESPI_15s_1s_0s)
Finished factoring (Time elapsed 0h:00m:05s; Memory used current: 63MB peak: 63MB)

@N:BN116 : rx_async.v(1415) | Removing sequential instance CoreUARTapb_0.CUARTO1II.CUARTIl1.CUARTOlI of view:PrimLib.dffs(prim) because there are no references to its outputs 
@N:BN116 : rx_async.v(1415) | Removing sequential instance CoreUARTapb_0.CUARTO1II.CUARTIl1.CUARTO1l_1 of view:PrimLib.dffr(prim) because there are no references to its outputs 
@N:BN116 : corei2creal.v(5507) | Removing sequential instance COREI2C_1.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CI1Il of view:PrimLib.dffs(prim) because there are no references to its outputs 
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:05s; Memory used current: 62MB peak: 64MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:05s; Memory used current: 63MB peak: 66MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:06s; Memory used current: 63MB peak: 66MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:06s; Memory used current: 63MB peak: 66MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:06s; Memory used current: 63MB peak: 66MB)

Finished preparing to map (Time elapsed 0h:00m:07s; Memory used current: 70MB peak: 71MB)


High Fanout Net Report
**********************

Driver Instance / Pin Name                             Fanout, notes                   
---------------------------------------------------------------------------------------
mycore_0.MSS_ADLIB_INST / M2FRESETn                    343 : 343 asynchronous set/reset
COREI2C_0.genblk13.CI2CIlI[0].ui2c.CI2COI0I[3] / Q     33                              
CORESPI_0.CSPIOl.CSPIlII / Q                           31                              
CoreUARTapb_0.CUARTO1II.CUARTl00.CUARTl0 / Q           28                              
COREI2C_0.genblk13.CI2CIlI[0].ui2c.CI2CIO0I[3] / Q     26                              
=======================================================================================

@N:FP130 :  | Promoting Net CORESPI_0.CSPIOl.genblk44\.genblk45\.CSPII1l.un2_busy on CLKINT  CORESPI_0.CSPIOl.genblk44\.genblk45\.CSPII1l.un2_busy_inferred_clock  
Replicating Sequential Instance COREI2C_0.genblk13.CI2CIlI[0].ui2c.CI2CIO0I[3], fanout 26 segments 2
Replicating Sequential Instance CoreUARTapb_0.CUARTO1II.CUARTl00.CUARTl0, fanout 28 segments 2
Replicating Sequential Instance CORESPI_0.CSPIOl.CSPIlII, fanout 31 segments 2
Replicating Sequential Instance COREI2C_0.genblk13.CI2CIlI[0].ui2c.CI2COI0I[3], fanout 33 segments 2
Buffering mycore_0_FAB_CLK, fanout 348 segments 15
Finished technology mapping (Time elapsed 0h:00m:08s; Memory used current: 76MB peak: 77MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:08s; Memory used current: 76MB peak: 77MB)


Added 15 Buffers
Added 4 Cells via replication
	Added 4 Sequential Cells via replication
	Added 0 Combinational Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:08s; Memory used current: 76MB peak: 77MB)

Writing Analyst data base Z:\eecs373-f10\labs\lab6\files\serialAnalyzerFpga\synthesis\mytop.srm
Finished Writing Netlist Databases (Time elapsed 0h:00m:08s; Memory used current: 74MB peak: 77MB)

Writing EDIF Netlist and constraint files
D-2009.12A
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:09s; Memory used current: 75MB peak: 77MB)

@W:MT420 :  | Found inferred clock mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock with period 20.00ns. A user-defined clock should be declared on object "n:mycore_0_FAB_CLK" 

@W:MT420 :  | Found inferred clock spi_master|un2_busy_inferred_clock with period 20.00ns. A user-defined clock should be declared on object "n:CORESPI_0.CSPIOl.genblk44.genblk45.CSPII1l.un2_busy" 

@W:MT246 : mycore.v(181) | Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : mycore.v(62) | Blackbox MSS_APB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : mycore_tmp_mss_ccc_0_mss_ccc.v(97) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


##### START OF TIMING REPORT #####[
# Timing Report written on Sat Oct 09 10:41:03 2010
#


Top view:               mytop
Library name:           smartfusion
Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
Requested Frequency:    50.0 MHz
Wire load mode:         top
Wire load model:        smartfusion
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.. 



Performance Summary 
*******************


Worst slack in design: 3.047

                                                             Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock                                               Frequency     Frequency     Period        Period        Slack     Type         Group              
---------------------------------------------------------------------------------------------------------------------------------------------------------------
mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     50.0 MHz      59.0 MHz      20.000        16.953        3.047     inferred     Inferred_clkgroup_0
System                                                       50.0 MHz      67.1 MHz      20.000        14.901        5.099     system       default_clkgroup   
===============================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                                              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                  Ending                                                    |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock  mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock  |  20.000      3.047  |  No paths    -      |  No paths    -      |  No paths    -    
mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock  spi_master|un2_busy_inferred_clock                        |  No paths    -      |  No paths    -      |  Diff grp    -      |  No paths    -    
spi_master|un2_busy_inferred_clock                        mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock  |  No paths    -      |  No paths    -      |  No paths    -      |  Diff grp    -    
==========================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                     Starting                                                                                            Arrival          
Instance                                             Reference                                                    Type         Pin     Net               Time        Slack
                                                     Clock                                                                                                                
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[1]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       CI2CIO0I[1]       0.580       3.047
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[2]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     Q       CI2CIO0I[2]       0.580       3.311
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[4]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1P0     Q       CI2CIO0I[4]       0.580       3.909
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[0]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1P0     Q       CI2CIO0I[0]       0.737       3.973
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I_0[3] mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1P0     Q       CI2CIO0I_0[3]     0.580       4.129
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CllIl[1]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1P0       Q       CI2CllIl[1]       0.737       4.265
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CllIl[2]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1P0       Q       CI2CllIl[2]       0.737       4.404
COREI2C_1.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CllIl[2]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1P0       Q       CI2CllIl[2]       0.737       4.538
COREI2C_1.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CllIl[1]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1P0       Q       CI2CllIl[1]       0.737       4.543
COREI2C_1.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CllIl[3]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1P0       Q       CI2CllIl[3]       0.580       6.015
==========================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                     Starting                                                                                             Required          
Instance                                             Reference                                                    Type         Pin     Net                Time         Slack
                                                     Clock                                                                                                                  
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[0]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1P0     E       N_912              19.392       3.047
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[1]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     E       N_912              19.392       3.047
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[2]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     E       N_912              19.392       3.047
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[3]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1P0     E       N_912              19.392       3.047
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[4]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1P0     E       N_912              19.392       3.047
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I_0[3] mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1P0     E       N_912              19.392       3.047
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CI0lI[2]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1C0       D       CI2CI0lI_ns[2]     19.427       3.130
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[3]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1P0     D       CI2CIO0I_20[3]     19.427       3.137
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I_0[3] mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1P0     D       CI2CIO0I_20[3]     19.427       3.137
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[1]   mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock     DFN1E1C0     D       CI2CIO0I_20[1]     19.496       3.856
============================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      20.000
    - Setup time:                            0.608
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         19.392

    - Propagation time:                      16.345
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     3.047

    Number of logic level(s):                8
    Starting point:                          COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[1] / Q
    Ending point:                            COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[0] / E
    The start point is clocked by            mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock [rising] on pin CLK
    The end   point is clocked by            mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock [rising] on pin CLK

Instance / Net                                                            Pin      Pin               Arrival     No. of    
Name                                                         Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[1]           DFN1E1C0     Q        Out     0.580     0.580       -         
CI2CIO0I[1]                                                  Net          -        -       2.409     -           22        
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I_RNIHH31[2]   OR2B         B        In      -         2.989       -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I_RNIHH31[2]   OR2B         Y        Out     0.516     3.505       -         
N_235                                                        Net          -        -       1.639     -           8         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I_RNI84L1[0]   OR2          A        In      -         5.144       -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I_RNI84L1[0]   OR2          Y        Out     0.507     5.652       -         
CI2ClO0I_3_sn_N_37                                           Net          -        -       1.279     -           5         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I_RNI2372_0[3] NOR2         A        In      -         6.931       -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I_RNI2372_0[3] NOR2         Y        Out     0.507     7.438       -         
N_521                                                        Net          -        -       1.184     -           4         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I_RNIT5P2[4]   OR2A         A        In      -         8.622       -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I_RNIT5P2[4]   OR2A         Y        Out     0.537     9.159       -         
CI2ClI0I152                                                  Net          -        -       1.184     -           4         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CI1Ol_RNIFD5P      NOR3C        C        In      -         10.342      -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CI1Ol_RNIFD5P      NOR3C        Y        Out     0.641     10.984      -         
un1_CI2ClO0I262_2                                            Net          -        -       0.386     -           2         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CI1Ol_RNIH0JH1_0   AO1A         B        In      -         11.370      -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CI1Ol_RNIH0JH1_0   AO1A         Y        Out     0.598     11.967      -         
un1_CI2Cl1lI_1                                               Net          -        -       1.639     -           8         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CI1Ol_RNIOQ1P1     NOR2         A        In      -         13.606      -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CI1Ol_RNIOQ1P1     NOR2         Y        Out     0.507     14.114      -         
N_918                                                        Net          -        -       0.322     -           1         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CI1Ol_RNIS9DC4     OA1B         C        In      -         14.435      -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CI1Ol_RNIS9DC4     OA1B         Y        Out     0.487     14.922      -         
N_912                                                        Net          -        -       1.423     -           6         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIO0I[0]           DFN1E1P0     E        In      -         16.345      -         
===========================================================================================================================
Total path delay (propagation time + setup) of 16.953 is 5.490(32.4%) logic and 11.464(67.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                            Starting                                                                          Arrival          
Instance                    Reference     Type        Pin              Net                                    Time        Slack
                            Clock                                                                                              
-------------------------------------------------------------------------------------------------------------------------------
mycore_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[4]      mycore_0_MSS_MASTER_APB_PADDR_\[4\]    0.000       3.465
mycore_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[2]      mycore_0_MSS_MASTER_APB_PADDR_\[2\]    0.000       3.837
mycore_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[0]      mycore_0_MSS_MASTER_APB_PADDR_\[0\]    0.000       4.080
mycore_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[1]      mycore_0_MSS_MASTER_APB_PADDR_\[1\]    0.000       4.220
mycore_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[3]      mycore_0_MSS_MASTER_APB_PADDR_\[3\]    0.000       4.586
mycore_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[11]     mycore_0_MSS_MASTER_APB_PADDR_\[11\]   0.000       4.814
mycore_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[9]      mycore_0_MSS_MASTER_APB_PADDR_\[9\]    0.000       4.847
mycore_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[12]     mycore_0_MSS_MASTER_APB_PADDR_\[12\]   0.000       4.953
mycore_0.MSS_ADLIB_INST     System        MSS_APB     MSSPENABLE       CoreAPB3_0_APBmslave0_PENABLE          0.000       5.000
mycore_0.MSS_ADLIB_INST     System        MSS_APB     MSSPADDR[10]     mycore_0_MSS_MASTER_APB_PADDR_\[10\]   0.000       5.052
===============================================================================================================================


Ending Points with Worst Slack
******************************

                                                   Starting                                                     Required          
Instance                                           Reference     Type         Pin     Net                       Time         Slack
                                                   Clock                                                                          
----------------------------------------------------------------------------------------------------------------------------------
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl    System        DFN1E1P0     D       CI2CIIOl_23_iv            19.427       3.465
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CII0I[0] System        DFN1E1C0     E       un1_CI2CII0I_2_sqmuxa     19.392       3.861
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CII0I[1] System        DFN1E1C0     E       un1_CI2CII0I_2_sqmuxa     19.392       3.861
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CII0I[2] System        DFN1E1C0     E       un1_CI2CII0I_2_sqmuxa     19.392       3.861
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CII0I[3] System        DFN1E1C0     E       un1_CI2CII0I_2_sqmuxa     19.392       3.861
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CII0I[4] System        DFN1E1C0     E       un1_CI2CII0I_2_sqmuxa     19.392       3.861
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CII0I[5] System        DFN1E1C0     E       un1_CI2CII0I_2_sqmuxa     19.392       3.861
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CII0I[6] System        DFN1E1C0     E       un1_CI2CII0I_2_sqmuxa     19.392       3.861
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CII0I[7] System        DFN1E1C0     E       un1_CI2CII0I_2_sqmuxa     19.392       3.861
COREI2C_1.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CII0I[0] System        DFN1E1C0     E       un1_CI2CII0I_2_sqmuxa     19.392       4.162
==================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      20.000
    - Setup time:                            0.573
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         19.427

    - Propagation time:                      15.961
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 3.465

    Number of logic level(s):                10
    Starting point:                          mycore_0.MSS_ADLIB_INST / MSSPADDR[4]
    Ending point:                            COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            mytop|mycore_0.MSS_CCC_0.mycore_0_FAB_CLK_inferred_clock [rising] on pin CLK

Instance / Net                                                          Pin             Pin               Arrival     No. of    
Name                                                       Type         Name            Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------
mycore_0.MSS_ADLIB_INST                                    MSS_APB      MSSPADDR[4]     Out     0.000     0.000       -         
mycore_0_MSS_MASTER_APB_PADDR_\[4\]                        Net          -               -       2.037     -           13        
CoreUARTapb_0.CUARTllII\.CUARTl0OI12_1                     NOR2         A               In      -         2.037       -         
CoreUARTapb_0.CUARTllII\.CUARTl0OI12_1                     NOR2         Y               Out     0.507     2.544       -         
CUARTl0OI12_1                                              Net          -               -       0.386     -           2         
COREI2C_1.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIll\.un4_PRDATANOR3C        A               In      -         2.930       -         
COREI2C_1.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIll\.un4_PRDATANOR3C        Y               Out     0.525     3.455       -         
un4_PRDATA                                                 Net          -               -       2.263     -           18        
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIll\.CI2CII0I60OR3C         C               In      -         5.718       -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIll\.CI2CII0I60OR3C         Y               Out     0.666     6.383       -         
CI2CII0I60                                                 Net          -               -       2.127     -           15        
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CI1Ol_RNINC4B3   OR2B         A               In      -         8.511       -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CI1Ol_RNINC4B3   OR2B         Y               Out     0.514     9.025       -         
CI2CII0I_0_sqmuxa                                          Net          -               -       1.184     -           4         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl_RNO_6      NOR2A        A               In      -         10.209      -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl_RNO_6      NOR2A        Y               Out     0.516     10.725      -         
CI2CIIOl_1_sqmuxa_0                                        Net          -               -       0.322     -           1         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl_RNO_5      AO1C         C               In      -         11.046      -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl_RNO_5      AO1C         Y               Out     0.655     11.701      -         
CI2CIIOl_1_sqmuxa                                          Net          -               -       0.322     -           1         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl_RNO_4      NOR2A        A               In      -         12.023      -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl_RNO_4      NOR2A        Y               Out     0.627     12.650      -         
un1_CI2Cl1lI_5_0                                           Net          -               -       0.322     -           1         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl_RNO_2      NOR2B        B               In      -         12.972      -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl_RNO_2      NOR2B        Y               Out     0.627     13.599      -         
un1_CI2Cl1lI_5_1                                           Net          -               -       0.322     -           1         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl_RNO_1      AOI1         A               In      -         13.921      -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl_RNO_1      AOI1         Y               Out     0.911     14.832      -         
CI2CIIOl_li_m                                              Net          -               -       0.322     -           1         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl_RNO        OA1B         C               In      -         15.153      -         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl_RNO        OA1B         Y               Out     0.487     15.640      -         
CI2CIIOl_23_iv                                             Net          -               -       0.322     -           1         
COREI2C_0.genblk13\.CI2CIlI\[0\]\.ui2c.CI2CIIOl            DFN1E1P0     D               In      -         15.961      -         
================================================================================================================================
Total path delay (propagation time + setup) of 16.535 is 6.609(40.0%) logic and 9.926(60.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A2F200M3F_FBGA256_Std
Report for cell mytop.verilog
  Core Cell usage:
              cell count     area count*area
              AND2     3      1.0        3.0
               AO1    18      1.0       18.0
              AO1A    22      1.0       22.0
              AO1B    32      1.0       32.0
              AO1C    18      1.0       18.0
              AO1D     9      1.0        9.0
              AOI1    24      1.0       24.0
             AOI1B    70      1.0       70.0
              AOI5     1      1.0        1.0
              AX1A     2      1.0        2.0
              AX1B     2      1.0        2.0
              AX1C     5      1.0        5.0
              AX1D     3      1.0        3.0
              AX1E     3      1.0        3.0
              AXO1     1      1.0        1.0
             AXOI1     1      1.0        1.0
             AXOI4     1      1.0        1.0
             AXOI5     1      1.0        1.0
             AXOI7     1      1.0        1.0
              BUFF    15      1.0       15.0
            CLKINT     1      0.0        0.0
               GND    17      0.0        0.0
               INV     6      1.0        6.0
              MAJ3     1      1.0        1.0
            MSSINT     1      0.0        0.0
           MSS_APB     1      0.0        0.0
           MSS_CCC     1      0.0        0.0
               MX2    53      1.0       53.0
              MX2A     6      1.0        6.0
              MX2B     8      1.0        8.0
              MX2C    42      1.0       42.0
             NAND2     2      1.0        2.0
              NOR2    46      1.0       46.0
             NOR2A    78      1.0       78.0
             NOR2B   109      1.0      109.0
              NOR3    20      1.0       20.0
             NOR3A    29      1.0       29.0
             NOR3B    32      1.0       32.0
             NOR3C    71      1.0       71.0
               OA1    29      1.0       29.0
              OA1A    19      1.0       19.0
              OA1B    18      1.0       18.0
              OA1C    15      1.0       15.0
              OAI1     9      1.0        9.0
               OR2    74      1.0       74.0
              OR2A   103      1.0      103.0
              OR2B   132      1.0      132.0
               OR3    23      1.0       23.0
              OR3A    28      1.0       28.0
              OR3B    36      1.0       36.0
              OR3C    68      1.0       68.0
               VCC    17      0.0        0.0
               XA1     6      1.0        6.0
              XA1A     6      1.0        6.0
              XA1B     8      1.0        8.0
              XA1C     5      1.0        5.0
              XAI1     4      1.0        4.0
             XAI1A     1      1.0        1.0
             XNOR2    18      1.0       18.0
             XNOR3     1      1.0        1.0
               XO1     1      1.0        1.0
              XOR2    21      1.0       21.0
              ZOR3     2      1.0        2.0


            DFN1C0    86      1.0       86.0
          DFN1E0C0    48      1.0       48.0
          DFN1E0P0     6      1.0        6.0
          DFN1E1C0   152      1.0      152.0
          DFN1E1P0    20      1.0       20.0
            DFN1P0    35      1.0       35.0
              DLN0     4      1.0        4.0
                   -----          ----------
             TOTAL  1751              1713.0


  IO Cell usage:
              cell count
             BIBUF     1
             INBUF     2
         INBUF_MSS     2
        MSS_XTLOSC     1
            OUTBUF    12
        OUTBUF_MSS     1
                   -----
             TOTAL    19


Core Cells         : 1713 of 4608 (37%)
IO Cells           : 19 of 66 (29%)

  RAM/ROM Usage Summary
Block Rams : 0 of 8 (0%)

Mapper successful!
Process took 0h:00m:13s realtime, 0h:00m:09s cputime
# Sat Oct 09 10:41:03 2010

###########################################################]