#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct  6 2010
#install: C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1
#OS: Windows XP 5.1
#Hostname: EECS373-07

#Implementation: synthesis

#Tue Sep 27 13:55:17 2011

$ Start of Compile
#Tue Sep 27 13:55:17 2011

Synopsys Verilog Compiler, version comp520rcp1, Build 028R, built Sep 23 2010
@N: :  | Running in 32-bit mode 
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

@I::"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v"
@I::"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v"
@I::"C:\Documents and Settings\373a\Desktop\lab4fpga\hdl\ReadSW_WriteLED.v"
@I::"C:\Documents and Settings\373a\Desktop\lab4fpga\hdl\ReadSW_WriteLED_wrp.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module ReadSW_WriteLED_wrp
@N:CG364 : ReadSW_WriteLED.v(52) | Synthesizing module Decoder3to8

@N:CG364 : ReadSW_WriteLED.v(3) | Synthesizing module ReadSW_WriteLED

@N:CG364 : ReadSW_WriteLED_wrp.v(3) | Synthesizing module ReadSW_WriteLED_wrp

@W:CS149 : ReadSW_WriteLED_wrp.v(39) | Port width mismatch for port subAddr.  Formal has width 8, Actual 9
@W:CL247 : ReadSW_WriteLED_wrp.v(19) | Input port bit 8 of PADDR[8:0] is unused

@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[3] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[4] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[5] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[6] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[7] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[8] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[9] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[10] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[11] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[12] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[13] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[14] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[15] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[16] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[17] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[18] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[19] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[20] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[21] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[22] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[23] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[24] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[25] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[26] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[27] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[28] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[29] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[30] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit data_out[31] is always 0, optimizing ...
@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 31 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 30 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 29 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 28 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 27 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 26 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 25 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 24 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 23 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 22 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 21 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 20 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 19 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 18 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 17 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 16 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 15 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 14 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 13 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 12 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 11 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 10 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 9 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 8 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 7 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 6 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 5 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 4 of data_out[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 3 of data_out[31:0] 

@W:CL246 : ReadSW_WriteLED.v(14) | Input port bits 7 to 4 of subAddr[7:0] are unused

@W:CL246 : ReadSW_WriteLED.v(14) | Input port bits 1 to 0 of subAddr[7:0] are unused

@W:CL246 : ReadSW_WriteLED.v(16) | Input port bits 31 to 3 of data_in[31:0] are unused

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Sep 27 13:55:17 2011

###########################################################]

Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 54MB peak: 55MB) Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 54MB peak: 55MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 54MB peak: 55MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 54MB peak: 55MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 54MB peak: 55MB) Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 54MB peak: 55MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 54MB peak: 55MB) Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 54MB peak: 55MB) @N:FP130 : | Promoting Net PCLK_c on CLKBUF PCLK_pad Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 54MB peak: 55MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 54MB peak: 55MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 54MB peak: 55MB) Writing Analyst data base C:\Documents and Settings\373a\Desktop\lab4fpga\synthesis\ReadSW_WriteLED_wrp.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 55MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 55MB) @W:MT420 : | Found inferred clock ReadSW_WriteLED_wrp|PCLK with period 10.00ns. A user-defined clock should be declared on object "p:PCLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Sep 27 11:49:41 2011 # Top view: ReadSW_WriteLED_wrp Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: 5.245 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------- ReadSW_WriteLED_wrp|PCLK 100.0 MHz 210.3 MHz 10.000 4.755 5.245 inferred Inferred_clkgroup_0 =============================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------ ReadSW_WriteLED_wrp|PCLK ReadSW_WriteLED_wrp|PCLK | 10.000 5.245 | No paths - | No paths - | No paths - ========================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: ReadSW_WriteLED_wrp|PCLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------- ReadSW_WriteLED_0.led_reg[0] ReadSW_WriteLED_wrp|PCLK DFN1 Q led_reg[0] 0.737 5.245 ReadSW_WriteLED_0.led_reg[1] ReadSW_WriteLED_wrp|PCLK DFN1 Q led_reg[1] 0.737 5.245 ReadSW_WriteLED_0.led_reg[2] ReadSW_WriteLED_wrp|PCLK DFN1 Q led_reg[2] 0.737 5.245 =============================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------- ReadSW_WriteLED_0.led_reg[0] ReadSW_WriteLED_wrp|PCLK DFN1 D led_reg_RNO[0] 9.427 5.245 ReadSW_WriteLED_0.led_reg[1] ReadSW_WriteLED_wrp|PCLK DFN1 D led_reg_RNO[1] 9.427 5.245 ReadSW_WriteLED_0.led_reg[2] ReadSW_WriteLED_wrp|PCLK DFN1 D led_reg_RNO[2] 9.427 5.245 ReadSW_WriteLED_0.data_out_1[0] ReadSW_WriteLED_wrp|PCLK DFN1E0 D data_out_7[0] 9.427 6.088 ReadSW_WriteLED_0.data_out_1[1] ReadSW_WriteLED_wrp|PCLK DFN1E0 D data_out_7[1] 9.427 6.088 ReadSW_WriteLED_0.data_out_1[2] ReadSW_WriteLED_wrp|PCLK DFN1E0 D data_out_7[2] 9.427 6.145 ========================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 4.181 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 5.245 Number of logic level(s): 2 Starting point: ReadSW_WriteLED_0.led_reg[0] / Q Ending point: ReadSW_WriteLED_0.led_reg[0] / D The start point is clocked by ReadSW_WriteLED_wrp|PCLK [rising] on pin CLK The end point is clocked by ReadSW_WriteLED_wrp|PCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------- ReadSW_WriteLED_0.led_reg[0] DFN1 Q Out 0.737 0.737 - led_reg[0] Net - - 1.708 - 10 ReadSW_WriteLED_0.led_reg_RNO_0[0] MX2 A In - 2.445 - ReadSW_WriteLED_0.led_reg_RNO_0[0] MX2 Y Out 0.579 3.024 - N_12 Net - - 0.322 - 1 ReadSW_WriteLED_0.led_reg_RNO[0] NOR2B A In - 3.346 - ReadSW_WriteLED_0.led_reg_RNO[0] NOR2B Y Out 0.514 3.860 - led_reg_RNO[0] Net - - 0.322 - 1 ReadSW_WriteLED_0.led_reg[0] DFN1 D In - 4.181 - ================================================================================================== Total path delay (propagation time + setup) of 4.755 is 2.403(50.5%) logic and 2.351(49.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F200M3F_FBGA256_Std Report for cell ReadSW_WriteLED_wrp.verilog Core Cell usage: cell count area count*area GND 3 0.0 0.0 MX2 5 1.0 5.0 NOR2B 4 1.0 4.0 NOR3A 1 1.0 1.0 NOR3C 1 1.0 1.0 OA1B 1 1.0 1.0 OR3 1 1.0 1.0 OR3A 3 1.0 3.0 OR3B 3 1.0 3.0 OR3C 2 1.0 2.0 VCC 3 0.0 0.0 DFN1 3 1.0 3.0 DFN1E0 3 1.0 3.0 ----- ---------- TOTAL 33 27.0 IO Cell usage: cell count CLKBUF 1 INBUF 11 OUTBUF 42 ----- TOTAL 54 Core Cells : 27 of 4608 (1%) IO Cells : 54 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Sep 27 11:49:41 2011 ###########################################################]