#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 #install: C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1 #OS: Windows XP 5.1 #Hostname: EECS373-07 #Implementation: synthesis #Tue Sep 27 22:24:25 2011 $ Start of Compile #Tue Sep 27 22:24:25 2011 Synopsys Verilog Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 @N: : | Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @I::"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v" @I::"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v" @I::"C:\Documents and Settings\373a\Desktop\lab4fpga\hdl\ReadSW_WriteLED.v" @I::"C:\Documents and Settings\373a\Desktop\lab4fpga\hdl\ReadSW_WriteLED_wrp.v" @I::"C:\Documents and Settings\373a\Desktop\lab4fpga\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v" @I::"C:\Documents and Settings\373a\Desktop\lab4fpga\component\work\lab4_mss\MSS_CCC_0\lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v" @I::"C:\Documents and Settings\373a\Desktop\lab4fpga\component\work\lab4_mss\mss_tshell.v" @I::"C:\Documents and Settings\373a\Desktop\lab4fpga\component\work\lab4_mss\lab4_mss.v" @I::"C:\Documents and Settings\373a\Desktop\lab4fpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v" @I::"C:\Documents and Settings\373a\Desktop\lab4fpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v" @I::"C:\Documents and Settings\373a\Desktop\lab4fpga\component\work\lab4_top\lab4_top.v" Verilog syntax check successful! File C:\Documents and Settings\373a\Desktop\lab4fpga\hdl\ReadSW_WriteLED.v changed - recompiling File C:\Documents and Settings\373a\Desktop\lab4fpga\hdl\ReadSW_WriteLED_wrp.v changed - recompiling File C:\Documents and Settings\373a\Desktop\lab4fpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v changed - recompiling File C:\Documents and Settings\373a\Desktop\lab4fpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v changed - recompiling File C:\Documents and Settings\373a\Desktop\lab4fpga\component\work\lab4_top\lab4_top.v changed - recompiling Selecting top level module lab4_top @W:CG775 : coreapb3.v(13) | Found Component CoreAPB3 in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(13) | Synthesizing module CAPB3O @N:CG364 : coreapb3.v(13) | Synthesizing module CoreAPB3 APB_DWIDTH=6'b100000 RANGESIZE=21'b000000000000100000000 IADDR_ENABLE=1'b0 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 CAPB3O1I=32'b00000000000000000000000000001000 CAPB3I1I=32'b00000000000000000000000000001000 CAPB3l1I=8'b00001100 CAPB3OOl=8'b00001000 CAPB3IOl=8'b00000100 CAPB3lOl=8'b00000000 CAPB3OIl=8'b00000100 CAPB3IIl=8'b00000000 CAPB3lIl=8'b00000000 CAPB3Oll=16'b0000000000000001 CAPB3Ill=16'b0000000000000000 CAPB3lll=16'b0000000000000000 CAPB3O0l=16'b0000000000000000 CAPB3I0l=16'b0000000000000000 CAPB3l0l=16'b0000000000000000 CAPB3O1l=16'b0000000000000000 CAPB3I1l=16'b0000000000000000 CAPB3l1l=16'b0000000000000000 CAPB3OO0=16'b0000000000000000 CAPB3IO0=16'b0000000000000000 CAPB3lO0=16'b0000000000000000 CAPB3OI0=16'b0000000000000000 CAPB3II0=16'b0000000000000000 CAPB3lI0=16'b0000000000000000 CAPB3Ol0=16'b0000000000000000 Generated name = CoreAPB3_Z1 @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC @N:CG364 : ReadSW_WriteLED.v(52) | Synthesizing module Decoder3to8 @N:CG364 : ReadSW_WriteLED.v(3) | Synthesizing module ReadSW_WriteLED @N:CG364 : ReadSW_WriteLED_wrp.v(3) | Synthesizing module ReadSW_WriteLED_wrp @W:CS149 : ReadSW_WriteLED_wrp.v(39) | Port width mismatch for port bus_addr. Formal has width 8, Actual 9 @N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS @N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC @N:CG364 : smartfusion.v(2566) | Synthesizing module RCOSC @N:CG364 : smartfusion.v(1133) | Synthesizing module GND @N:CG364 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module lab4_mss_tmp_MSS_CCC_0_MSS_CCC @N:CG364 : mss_tshell.v(1) | Synthesizing module MSS_APB @N:CG364 : lab4_mss.v(5) | Synthesizing module lab4_mss @N:CG364 : lab4_top.v(5) | Synthesizing module lab4_top @W:CL157 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(48) | Input MAINXIN is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused @W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused @W:CL247 : ReadSW_WriteLED_wrp.v(19) | Input port bit 8 of PADDR[8:0] is unused @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[3] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[4] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[5] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[6] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[7] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[8] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[9] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[10] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[11] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[12] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[13] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[14] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[15] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[16] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[17] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[18] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[19] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[20] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[21] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[22] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[23] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[24] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[25] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[26] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[27] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[28] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[29] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[30] is always 0, optimizing ... @W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[31] is always 0, optimizing ... @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 31 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 30 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 29 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 28 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 27 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 26 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 25 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 24 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 23 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 22 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 21 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 20 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 19 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 18 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 17 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 16 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 15 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 14 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 13 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 12 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 11 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 10 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 9 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 8 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 7 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 6 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 5 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 4 of bus_read_data[31:0] @W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 3 of bus_read_data[31:0] @W:CL246 : ReadSW_WriteLED.v(14) | Input port bits 7 to 4 of bus_addr[7:0] are unused @W:CL246 : ReadSW_WriteLED.v(14) | Input port bits 1 to 0 of bus_addr[7:0] are unused @W:CL246 : ReadSW_WriteLED.v(16) | Input port bits 31 to 3 of bus_write_data[31:0] are unused @W:CL246 : coreapb3.v(217) | Input port bits 23 to 12 of PADDR[23:0] are unused @W:CL159 : coreapb3.v(208) | Input PRESETN is unused @W:CL159 : coreapb3.v(210) | Input PCLK is unused @W:CL159 : coreapb3.v(356) | Input PRDATAS1 is unused @W:CL159 : coreapb3.v(363) | Input PRDATAS2 is unused @W:CL159 : coreapb3.v(370) | Input PRDATAS3 is unused @W:CL159 : coreapb3.v(377) | Input PRDATAS4 is unused @W:CL159 : coreapb3.v(384) | Input PRDATAS5 is unused @W:CL159 : coreapb3.v(391) | Input PRDATAS6 is unused @W:CL159 : coreapb3.v(398) | Input PRDATAS7 is unused @W:CL159 : coreapb3.v(405) | Input PRDATAS8 is unused @W:CL159 : coreapb3.v(412) | Input PRDATAS9 is unused @W:CL159 : coreapb3.v(419) | Input PRDATAS10 is unused @W:CL159 : coreapb3.v(426) | Input PRDATAS11 is unused @W:CL159 : coreapb3.v(433) | Input PRDATAS12 is unused @W:CL159 : coreapb3.v(440) | Input PRDATAS13 is unused @W:CL159 : coreapb3.v(447) | Input PRDATAS14 is unused @W:CL159 : coreapb3.v(454) | Input PRDATAS15 is unused @W:CL159 : coreapb3.v(458) | Input PREADYS1 is unused @W:CL159 : coreapb3.v(460) | Input PREADYS2 is unused @W:CL159 : coreapb3.v(462) | Input PREADYS3 is unused @W:CL159 : coreapb3.v(464) | Input PREADYS4 is unused @W:CL159 : coreapb3.v(466) | Input PREADYS5 is unused @W:CL159 : coreapb3.v(468) | Input PREADYS6 is unused @W:CL159 : coreapb3.v(470) | Input PREADYS7 is unused @W:CL159 : coreapb3.v(472) | Input PREADYS8 is unused @W:CL159 : coreapb3.v(474) | Input PREADYS9 is unused @W:CL159 : coreapb3.v(476) | Input PREADYS10 is unused @W:CL159 : coreapb3.v(478) | Input PREADYS11 is unused @W:CL159 : coreapb3.v(480) | Input PREADYS12 is unused @W:CL159 : coreapb3.v(482) | Input PREADYS13 is unused @W:CL159 : coreapb3.v(484) | Input PREADYS14 is unused @W:CL159 : coreapb3.v(486) | Input PREADYS15 is unused @W:CL159 : coreapb3.v(490) | Input PSLVERRS1 is unused @W:CL159 : coreapb3.v(492) | Input PSLVERRS2 is unused @W:CL159 : coreapb3.v(494) | Input PSLVERRS3 is unused @W:CL159 : coreapb3.v(496) | Input PSLVERRS4 is unused @W:CL159 : coreapb3.v(498) | Input PSLVERRS5 is unused @W:CL159 : coreapb3.v(500) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.v(502) | Input PSLVERRS7 is unused @W:CL159 : coreapb3.v(504) | Input PSLVERRS8 is unused @W:CL159 : coreapb3.v(506) | Input PSLVERRS9 is unused @W:CL159 : coreapb3.v(508) | Input PSLVERRS10 is unused @W:CL159 : coreapb3.v(510) | Input PSLVERRS11 is unused @W:CL159 : coreapb3.v(512) | Input PSLVERRS12 is unused @W:CL159 : coreapb3.v(514) | Input PSLVERRS13 is unused @W:CL159 : coreapb3.v(516) | Input PSLVERRS14 is unused @W:CL159 : coreapb3.v(518) | Input PSLVERRS15 is unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Sep 27 22:24:26 2011 ###########################################################]