Branch Prediction Publications
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Jared Stark, Marius Evers, and Yale N. Patt,
"Variable Length Path Branch Prediction,"
Proceedings of the Eighth International Conference on Architectural
Support for Programming Languages and Operating Systems,
San Jose, October 1998
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Marius Evers, Sanjay J. Patel, Robert S. Chappell, and Yale N. Patt,
"Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work,"
Proceedings of the 25th International Symposium on Computer Architecture,
Barcelona, June 1998
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Po-Yung Chang, Eric Hao, and Yale N. Patt,
"Target Prediction for Indirect Jumps,"
Proceedings of the 24th International Symposium on Computer Architecture,
Denver, June 1997
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Eric Sprangle, Robert S. Chappell, Mitch Alsup, and Yale N. Patt,
"The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference,"
Proceedings of the 24th International Symposium on Computer Architecture,
Denver, June 1997
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Po-Yung Chang, Marius Evers, and Yale N. Patt,
"Improving Branch Prediction Accuracy by Reducing Pattern History
Table Interference,"
International Journal of Parallel Programming, 1997, vol 25,
num 5, pp. 339-362.
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Stephan Jourdan, Jared Stark, Tse-Hao Hsing, and Yale N. Patt,
"Recovery Requirements of Branch Prediction and Storage Structures in the Presence of
Mispredicted-Path Execution,"
International Journal of Parallel Programming, 1997, vol 25,
num 5, pp. 363-384.
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Stephan Jourdan, Tse-Hao Hsing, Jared Stark, and Yale N. Patt,
"The Effects of Mispredicted-Path Execution on Branch Prediction
Structures,"
International Conference on Parallel Architectures and Compilation
Techniques, Boston, MA, October, 1996.
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Po-Yung Chang, Marius Evers, and Yale N. Patt,
"Improving Branch Prediction Accuracy by Reducing Pattern History
Table Interference,"
International Conference on Parallel Architectures and Compilation
Techniques, Boston, MA, October, 1996.
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Marius Evers, Po-Yung Chang, and Yale N. Patt,
"Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence
of Context Switches,"
Proceedings, 23th International Symposium on Computer Architecture,
Philadelphia, PA, May, 1996.
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Po-Yung Chang, Eric Hao, and Yale N. Patt,
"Alternative Implementations of Hybrid Branch Predictors,"
Proceedings of the 28th ACM/IEEE International Symposium on Microarchitecture,
Ann Arbor, MI, 1995.
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Po-Yung Chang, Eric Hao, Yale N. Patt, and Pohua Chang,
"Using Predicated Execution to Improve the Performance of a Dynamically-Scheduled
Machine With Speculative Execution,"
International Journal of Parallel Programming, vol.24, 1996.
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Po-Yung Chang, Eric Hao, Yale N. Patt, and Pohua Chang,
"Using Predicated Execution to Improve the Performance of a Dynamically-Scheduled
Machine With Speculative Execution,"
International Conference on Parallel Architectures and Compilation
Techniques, Limassol, Cyprus, June, 1995.
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Po-Yung Chang, Eric Hao, Tse-Yu Yeh, and Yale Patt,
"Branch Classification: A New Mechanism for Improving Branch Predictor
Performance,"
International Journal of Parallel Programming, vol.24, 1996.
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Po-Yung Chang, Eric Hao, Tse-Yu Yeh, and Yale Patt,
"Branch Classification: A New Mechanism for Improving Branch Predictor Performance,"
Proceedings of the 27th International Symposium on Microarchitecture,
San Jose, California, November, 1994.
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Eric Hao, Po-Yung Chang, and Yale Patt,
"The Effect of Speculatively Updating Branch History on Branch Prediction Accuracy,
Revisited,"
Proceedings of the 27th International Symposium on Microarchitecture,
San Jose, California, November, 1994.
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Tse-Yu Yeh and Yale N. Patt,
"Branch History Table Indexing to Prevent Pipeline Bubbles in Wide-Issue
Superscalar Processors,"
Proceedings of the 26th International Symposium and workshop on
Microarchitecture, Austin, TX, December 1993.
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Tse-Yu Yeh, Deborah Marr, and Yale Patt,
"Increasing Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address
Cache,"
Proceedings of the 7th ACM International Conference on Supercomputing,
Tokyo, Japan, July, 1993.
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Tse-Yu Yeh and Yale N. Patt,
"A Comparison of Dynamic Branch Predictors that use Two Levels of
Branch History,"
Proceedings, 20th International Symposium on Computer Architecture,
San Diego, CA, May, 1993.
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Tse-Yu Yeh and Yale Patt,
"A Comprehensive Instruction Fetch Mechanism
for a Processor Supporting Speculative Execution,"
Proceedings, 25th International Symposium and workshop on
Microarchitecture, Portland OR, November, 1992.
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Tse-Yu Yeh and Yale Patt,
"Alternative Implementations of Two-Level Adaptive Training Branch
Prediction,"
Proceedings, 19th International Symposium on Computer Architecture,
Queensland, Australia, May, 1992.
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Tse-Yu Yeh and Yale Patt,
"Two-Level Adaptive Branch Prediction,"
Proceedings, 24th International Symposium and workshop on Microarchitecture,
Albuquerque, November, 1991.