Microarchitecture Publications
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Robert S. Chappell, Jared Stark, Sangwook P. Kim, Steven K. Reinhardt, and Yale N. Patt,
"Simultaneous
Subordinate Microthreading (SSMT),"
Proceedings of the 26th International Symposium on Computer Architecture, Altanta, May, 1999.
PAg Microcode
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Eric Hao, Po-Yung Chang, Marius Evers, and Yale N. Patt,
"Increasing the Instruction Fetch Rate via Block-Structured Instruction Set
Architectures,"
International Journal of Parallel Programming, Vol. 26, No. 4, 1998
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Jared Stark, Paul B. Racunas, and Yale N. Patt,
"Reducing
the Performance Impact of ICache Misses by Writing Instructions into the
Reservation Stations Out-of-Order,"
Proceedings of the 30th ACM/IEEE International Symposium on Microarchitecture,
Research Triangle Park, North Carolina, November, 1997.
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Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, and Jared
Stark,"
"One Billion Transistors, One Uniprocessor, One Chip,"
IEEE Computer, September, 1997.
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Eric Hao, Po-Yung Chang, Marius Evers, and Yale N. Patt,
"Increasing
the Instruction Fetch Rate via Block-Structured Instruction Set Architectures,"
Proceedings of the 29th ACM/IEEE International Symposium on Microarchitecture,
Paris, France, November, 1996.
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Yale N. Patt,
"The Microprocessor for Scientific Computing in the year 2000,"
IEEE Computational Science and Engineering, Summer 1996.
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Yale Patt,
"First, Let's Get the Uniprocessor Right,"
MicroDesign Resources, Microprocessor Report, August, 1996.
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Stephen Melvin and Yale N. Patt,
Enhancing Instruction Scheduling With a Block-Structured ISA,
International Journal of Parallel Programming, vol. 23, no.
3, 1995.
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Eric Sprangle and Yale N. Patt,
"Facilitating Superscalar Processing via a Combined Static/Dynamic
Register Renaming Scheme,"
Proceedings of the 27th International Symposium on Microarchitecture,
San Jose, California, November, 1994.
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Michael Butler and Yale Patt,
"A Comparative Performance Evaluation of Various State maintenance
Mechanisms,"
Proceedings of the 26th International Symposium and workshop on
Microarchitecture, Austin, TX, December 1993.
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Tse-Yu Yeh, Deborah Marr, and Yale Patt,
"Increasing Instruction Fetch Rate via Multiple Branch Prediction
and a Branch Address Cache,"
Proceedings of the 7th ACM International Conference on Supercomputing,
Tokyo, Japan, July, 1993.
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Michael Butler and Yale Patt,
"An Investigation of the Performance of Various Dynamic Scheduling
Techniques,"
Proceedings, 25th International Symposium and workshop on Microarchitecture,
Portland OR, November, 1992.
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Tse-Yu Yeh and Yale Patt,
"A Comprehensive Instruction Fetch Mechanism for a Processor Supporting
Speculative Execution,"
Proceedings, 25th International Symposium and workshop on Microarchitecture,
Portland OR, November, 1992.
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Michael Butler, David Dyer, and Yale Patt,
"Toward the Specification of an ISA for High Performance Computing
Engines -- Part I: The Hardware Perspective,"
Proceedings, 25th Hawaii International Conference on Systems Sciences,
Kauai, January, 1992.
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Michael Butler and Yale Patt,
"The Effect of Real Data Cache Behavior on the Performance of a
Microarchitecture that Supports Dynamic Scheduling,"
Proceedings, 24th International Symposium and workshop on Microarchitecture,
Albuquerque, November, 1991.
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M. Butler, T-Y Yeh, Y. Patt, M. Alsup, H. Scales, and M. Shebanow,
"Single Instruction Stream Parallelism is Greater than Two,"
Proceedings of the 18th International Symposium on Computer Architecture,
May, 1991.
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Stephen Melvin and Yale Patt,
"Exploiting Fine-Grained Parallelism through Combined Hardware and
Software Techniques,"
Proceedings of the 18th International Symposium on Computer Architecture,
May, 1991.
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Michael Butler and Yale Patt,
"An Area-efficient Register Alias Table for Implementing HPS,"
Proceedings of the International Conference on Parallel Processing,
August, 1990.