Seventh Annual Workshop on Modeling, Benchmarking and Simulation

MoBS 2011

Program now available

Held in conjunction with the 38^th Annual International Symposium on Computer Architecture

June 5, 2011

San Jose, CA

Program

· 9:00 - 9:05: Welcome by the organizers

· 9:05 - 10:00: Keynote

Modeling the Impact of Disruptive Technologies on System Architectures

Naveen Muralimanohar & Sheng Li (HP Labs)

The quest to achieve exascale machines by the end of this decade requires many disruptive changes to the system architecture and memory hierarchy. Many new technologies such as 3D stacking, optical interconnects, FinFET devices, etc., will play a large role in future systems. Future standalone processors will likely encompass more system components such as I/O controller, memory, etc. In addition, scaling limitations of DRAM and Flash require embracing new memory technologies. In the past, analytical modeling tools have played a key role in design space exploration by providing a quick estimate of power, area, and delay early in the design phase. With system architecture going through a major inflection point, this talk will discuss the requirements of future analytical modeling tools and potential pitfalls to avoid while using them for evaluation. Specifically, the talk will describe the critical role of the CACTI memory modeling tool and the McPAT processor modeling tool in designing future architectures and interesting opportunities to contribute enhancements to these tools.

Naveen Muralimanohar is a senior researcher in Intelligent Infrastructure Lab at HP Labs. His research focuses on designing reliable and efficient memory hierarchy and communication fabrics for high performance systems. He has published several influential papers on memory hierarchy and won best paper award for his work on energy efficient cache design. His work on large caches and CACTI tool appeared in IEEE Micro Top picks. He has co-authored over 20 technical papers, 15 patents (pending/received), and a book titled "Multi-core Cache Hierarchies". He received his Ph.D. in computer science from University of Utah and B.E in electrical engineering from University of Madras.

Sheng Li received his PhD in Electrical Engineering from the University of Notre Dame in 2010. He is currently with the Intelligent Infrastructure Lab at HP Labs. His research focuses on power efficient and scalable chip multiprocessor architectures, reliable and efficient memory sub-systems, and rapid circuit/device modeling. Sheng Li leads the McPAT (Manycore Power, Area, and Timing) modeling infrastructure (http://www.hpl.hp.com/research/mcpat/) and is one of the main contributors of the CACTI tool. He was also the leading architect of Lightweight Chip Multithreading (LCMT) in the DARPA HPCS project. He has co-authored more than 15 technical papers and 6 patents. In 2004, he was bestowed the Science and Technology Achievement Award by the Department of Education, Govt. of China.

· 10:00 - 10:30: Break

· 10:30 - 12:30: Technical Session

Modeling, Simulation and Optimization of Power and Performance of Data Centers

Reinaldo Bergamaschi, Leonardo Piga, Rodolfo Jardim de Azevedo, Sandro Rigo, Guido Araujo (Institute of Computing, Campinas State University, Brazil)

Joint Exploration of Hardware Prefetching and Bandwidth Partitioning in Chip Multiprocessors

Fang Liu and Yan Solihin (NC State)

TMAPP – Typical Mobile Applications Benchmark

Joseph Issa, Quoc Le, Soohong Min, Johann Steinbrecher, Rajesh Turlapati Silvia Figueira, JoAnne Holliday, Weijia Shang (Santa Clara University) Moenes Iskarous, Dharmesh Jani (Intel)

Impact of Java Application Server Evolution on Computer System Performance

Peng-Fei Chuang (Intel) Celal Ozturk (Univ. of Rhode Island) Khun Ban, Huijun Yan, Kingsum Chow (Intel) Resit Sendag (Univ. of Rhode Island)

· 12:30 - 12:35: Concluding remarks

Overview:

With few exceptions, simulation is the quantitative foundation for virtually all computer architecture research and design projects – from microarchitectural exploration to hardware and software trade-offs to processor and system design. However, its continued efficacy is limited by the need to model or compensate for problems such as increasing complexity (e.g., multiple cores and peripherals), additional critical constraints (e.g., power consumption, reliability, etc.), an ever-expanding design space (e.g., chip, system, and data center scale modeling), and benchmark suite quality and coverage.

Accordingly, the goals of this workshop are to accelerate the development of technologies that are necessary to support the research of future generation architectures and to encourage the advancement of “under-researched” areas in computer architecture measurement. Accordingly, this workshop places a special premium on novelty and on preliminary work. Topics of interest include, but are not limited to:

· System-level architecture modeling and measurement

· Data center level modeling and measurement

· Performance/energy/temperature/reliability measurement and analysis tools

· New or efficient techniques to model performance, power, temperature, reliability, etc.

· Simulation methodologies for multi-core and many-core architectures

· Simulator validation

· Development of parameterizable, flexible benchmarks

· New benchmark suites for emerging application areas

· Analytical and statistical modeling

Important Dates:

Paper Submission: Extended to April 7, 2011

Notification Date: April 29, 2011