Parallel Performance Project Research Paper

Research Paper

Utilizing Reuse Information in Data Cache Management
Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, and Matt Farrens
Proceedings of the 12th ACM International Conference on Supercomputing July, 1998

Abstract

As microprocessor speeds continue to outgrow memory subsystem speeds, minimizing the average data access time grows in importance. As current data caches are often poorly and inefficiently managed, a good management technique can improve the average data access time. This paper presents a comparative evaluation of two approaches that utilize reuse infor mation for more efficiently managing the first-level cache. While one approach is based on the effective address of the data being referenced, the other uses the program counter of the memory instruction generating the reference. Our evaluations show that using effective address reuse information performs better than using program counter reuse information. In addition, we show that the Victim cache performs best for multi-lateral caches with a direct-mapped main cache and high L2 cache latency, while the NTS (effective-address-based) approach performs better as the L2 latency decreases or the associativity of the main cache increases.