Parallel Performance Project Research Paper

Research Paper

Performance Issues in Integrating Temporality-Based Caching with Prefetching
Jude A. Rivers and Edward S. Davidson
Proceedings of the IFIP WG7.3 Int'l Conf. on Performance Theory, Measurement and Evaluation of Computer and Communication Systems (Performance'96), October 1996. Also appears as Performance Evaluation Vol 27&28 (1996) pp 175-188.

Abstract

This work evaluates the performance effectiveness of combining two techniques for improving cache hit rate and reducing memory traffic in small on-chip direct-mapped caches. Temporality-based caching is an efficient technique for reducing unnecessary cache block conflicts in direct-mapped caches, but does not address compulsory misses. Tagged prefetching is a known technique for controlling compulsory misses, but has the potential for introducing high block interference, cache pollution and increased memory traffic in small direct-mapped caches. We propose and evaluate a group of caching strategies that integrate various combinations of temporality-based caching and tagged prefetching. Some combinations show both a remarkable improvement in hit rate and a substantial reduction in memory traffic.