Parallel Performance Project Research Paper

Research Paper

Using Constraint Geometry to Determine Maximum Rate Pipeline Clocking
C.-H. Chang, E. S. Davidson and K. A. Sakallah
Digest of Technical Papers, IEEE International Conference on Computer-Aided Design (ICCAD), pp 142-148, Nov. 1992.

Abstract

Maximum rate pipeline clocking is an important subject in high performance system design. Previous work has been done in this field to model the behavior of a pipeline circuit and determine its optimum clock schedule using various methods. This report presents a new approach, using geometric information about the shape of the feasible region formed by pulse width, setup, and hold constraints, to determine the maximum rate for single phase pipeline clocking. The pipeline model uses level-sensitive latches as synchronizers and can allow wave pipelining. A program, Gpipe, implements this idea. I also use Gpipe to explore the effect of removing non-synchronizing and/or synchronizing latches on the maximum clock speed of the pipeline. Some examples and the theory behind this are shown in this report. Finally it is shown when and how the optimum clock speed of a pipeline can be increased by removing appropriate latches.