Parallel Performance Project Research Paper

Research Paper

Delay Balancing using Latches
C.-H. Chang and E. S. Davidson
Digest of Papers, Tau'95: 1995 ACM International Workshop on Timing issues in the Specification and Synthesis of Digital Systems, pp 66-73, Nov. 1995

Abstract

Delay elements are often added to improve performance of a wave-pipelined circuit by reducing the delay difference of the longest and the shortest paths. Unfortunately, precise delay elements that realize the exact delay needed are diffi cult to obtain. Instead we use latches for delay balancing, thereby providing more feasible and accurate circuit path delay control under the Min/Max delay model. A heuristic is developed to insert a sufficient number of latches into a com binational circuit to achieve a specified clock cycle time. Experiments on the ISCAS C85 benchmark illustrate this approach and its advantage.