Parallel Performance Project Research Paper

Research Paper

Maximum Rate Single-Phase Clocking of a Closed Pipeline including Wave Pipelining, Stoppability, and Startability
C.-H. Chang, E. S. Davidson and K. A. Sakallah
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 12, pp 1526-1545, December 1995

Abstract

Aggressive design using level-sensitive latches and wave pipelining has been proposed to meet the increasing need for higher performance digital systems. The optimal clocking problem for such designs has been formulated using an accurate timing model. However, this problem has been difficult to solve because of its nonconvex solution space. The best algorithms to date employ linear programs to solve an overconstrained case that has a convex solution space, yield ing suboptimal solutions to the general problem. A new efficient (cubic complexity) algorithm, Gpipe, exploits the geometric characteristics of the full nonconvex solution space to determine the maximum single-phase clocking rate for a closed pipeline with a specified degree of wave pipe lining.

Introducing or increasing wave pipelining by permanently enabling some latches is also inves tigated. Sufficient conditions have been found to identify which latches can be removed in this fashion so as to guarantee no decrease and permit a possible increase in the clock rate. Although increasing the degree of wave pipelining can result in faster clocking, wave pipelining is often avoided in design due to difficulties in stopping and restarting the pipeline under stall conditions without losing data, or in reduced rate testing of the circuit. To solve this problem, which has not previously been addressed, we present conditions and implementation methods that insure the stoppability and restartability of a wave pipeline.