PUMA

Design Optimization of a GaAs RISC Microprocessor with Area-Interconnect MCM Packaging

Principal Investigators:

Richard B. Brown, University of Michigan
Trevor Mudge, University of Michigan
Ronald J. Lomax, University of Michigan
Karem A. Sakallah, University of Michigan


CGaAs FXU (PowerPC Integer Processor)

Abstract:

The primary focus of this project is the development of a radiation-hard complementary GaAs (CGaAs), PowerPC microprocessor with flip-chip, area I/O packaging. This processor, called PUMA, is ideally suited to space applications because of its low power-delay product and excellent radiation hardness. We have partially tested a CMOS prototype of the PUMA architecture, and are ready to begin testing the CGaAs processor. We have analyzed the CGaAs technology to determine the most cost-effective scaling factor for each design rule; in this effort, we have developed a methodology and tools to help engineers also scale CMOS processes non-linearly.

We have developed and tested low-jitter PLL clock generators, current-mode I/O, and CAD tools for better leaf-cell design, logic synthesis, and minimization of cross-talk. We have developed new packaging capabilities, including a gold bumping process which produces bumps with pitches as small as 50 mm. Assembly of MCMs has begun at 3-M. The remainder of this project and an accompanying AASERT will complete the system design and demonstrate the prototype in a desktop computer.

This project is supported by the Advanced Research Projects Agency under ARPA/ARO Contract Number DAAH04-94-G-0327.

Recent Work (2/2004)

        PUMA FXU I/P Core download

Project Summary

Publications

Presentations

Chip Designs

Researchers

Corporate Partners

The University of Michigan

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