The University of Michigan
High-Performance Microprocessor Project
Aurora III Floating Point Unit
250 MHz, 300 SPECfp92 rating
500K transistors
16x16 mm2
40 instructions (MIPS R4000), including double-word loads/stores and integer multiply
Iterative 5 cycle Wallace tree multiplier (4-2 adders)
Pipelined 3 cycle add unit
Pipelined 2 cycle conversion unit
Iterative 19 cycle SRT-8 divide unit (not incl. with this version)
IEEE-754 compliant (4 rounding modes and exceptions)
Precise and higher performance real-time exception modes
Issue policy: in-order issue, out-of-order completion, 2 instructions per cycle
Data prefetching with unity stride
Instruction queue: 6 entries, predecoded
Load queue: 2 entries
ROB: 8 entries
Store queue: 2 entries
Result busses: 2
Verification via random testing
Functional units verified against actual workstation (>5M operations per unit)
FPU verified using self-checking random instruction sequences (>200M instructions)
Design-for-test inclues:
5 scan chains (4 data, 1 control)
Full read/write access to register file
Individual instructions are testable via scan paths
Speed testing requires only the 2 clock signals to operate at high frequency
5 students - 1.5 years
Chief designer:
Tom Huff
Additional students:
Ajay Chandna - sense-amplifier based register file (64x64, 4 read ports, 1 write port, 2ns)
Dave Kibler - conversion unit verification and cell library creation
Dave Putti - divide unit
Mike Riepe - multiply unit
PJ Sherhart - pads
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