The University of Michigan
High-Performance Microprocessor Project

Aurora I CPU

30 instructions
Fully functional ALU with Ling-modified adder
3-port 32x32 register file
Quick compare logic for branch determination
Scan chain comprised of all datapath latches
All instructions verified at 100MHz
60,500 transistors
11W power dissipation
Yield of ~20%
5 students - 5 months
1 known bug, related to the instruction address bus connection between core and pads

Principal Designers:

Ajay Chandna
Tom Hoy
Tom Huff
Rich Uhlig
Mike Upton

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