The University of Michigan
High-Performance Microprocessor Project

Aurora II CPU

180 MHz
160K transistors
Slightly smaller than Aurora I (13.9x7.8 mm2)
20W
1.6ns 32x32 3-port register file
1.7ns 32-bit Ling-modified carry-select adder
Primary and secondary cache support
Four modes of cache operation
Support for additional instructions, incl. exceptions and system calls
Interface to DEC Turbochannel bus
5 students - 1 year

Several design problems found during testing:

Power/ground short within pads (remedied by a second refab)
Clock phase error which limited frequency (also remedied by the second refab)
Two functional errors not uncovered by late verification

Chief designers:

Mike Upton
Tom Huff

Additional students:

PJ Sherhart
Phil Barker
Bob Mcvay
Taly Budescu

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