Table of Contents
A MICROARCHITECTURE FOR RESOURCE-LIMITED SUPERSCALAR MICROPROCESSORS
Overview
Motivation
Motivation
Goals of this Thesis
History of GaAs at U of M
Motorola 0.5 um CGaAs
CGaAs cross-section
Radiation-hard CGaAs
Low-cost Rad-hard CGaAs
CGaAs delay versus VDD
CGaAs DCFL
CGaAs Complementary Logic
CGaAs Domino Logic
CGaAs Digital Logic Families
CGaAs PowerPC ALU
CGaAs Design Challenges
POWER and PowerPC
POWER
PowerPC 601-620
G3-series: PowerPC 750
Philosophy of CGaAs PowerPC Microprocessor
PUMA System Block Diagram
PUMA System Details
Microarchitecture Optimizations
Simulation Environment
Baseline Microarchitecture
Instruction Prefetching
Instruction Prefetching (cont.)
Branch Prediction
Taxonomy of Branch Predictors
Branch Prediction (cont.)
Off-chip Data Cache
Instruction Translation
Superscalar Execution
Reservation Stations
Reorder Buffer
Microprocessor Configurations
Improvement over Baseline
Advantage over Pipeline
Computational Efficiency
Proposed FXU Microarchitecture
FXU Block Diagram
FXU Logical Pipeline
CMOS FXU I
FXU I Path Distribution
CMOS FXU I Microprocessor
CGaAs FXU II
FXU II Path Distribution
CGaAs FXU II Microprocessor
Computation Efficiency (revisited)
CGaAs Design Challenges
CGaAs v. CMOS (device)
CGaAs v. CMOS (fanout)
CGaAs v. CMOS (geometry)
CGaAs With Lower VT
Summary of CGaAs
Future Work
Contributions (microarchitecture)
Contributions (circuit)
Acknowledgements
|