Table of Contents
A Low-Cost, High-Bandwidth I/O Transceiver Based On Switched-Current Techniques
Motivation
Goals
Outline
Signaling Problem
Noise
Eye-Diagrams
Conventional Signaling
Source Synchronous Interface
Phase Jitter Limits Interface Performance
CGaAs Multichip PowerPC Microprocessor
Motorola 0.5 um CGaAs
Packaging Technology
Early CGaAs Work
Conventional Interfaces in CGaAs
CGaAs Test Chip
Measured Results: Process Monitor Stuctures
Eye Diagram
Scannable Transmitter/Receiver
Scannable Chip Measurements
Prototype MCM
Advanced CGaAs Circuits
Cascoded Switched-Current Termination
Active Current Mirror Termination
ACMT Implementation
Dynamic Biasing Network
Implementation
Simulation: Supply Mismatch
Simulated Performance
CGaAs Delay-Locked-Loop (DLL)
Design Details
Simulated Performance
Source Synchronous Interface
Interface Simulations
CMOS ACMT
CMOS Implementation
CMOS Dynamic Biasing Network
Dynamic Biasing Network: Supply Mismatch
Process Corners
Test Chip
Process Monitor
Output Pad Characteristic
Static Biasing Eye Diagram
Dynamic Biasing Eye Diagram
Measured Results
Relative Performance
Future Work
Contributions
Contributions
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