Table of Contents
Transistor Level Micro-Placement and Routing for Two-Dimensional Digital VLSI Cell Synthesis
VLSI Design 101
Outline
Part I
SIA Industry Roadmap
Productivity Gap
Hierarchical Design
Library Cell Design
The Future
Goal: On-Demand Cell Synthesis
1D Cell Synthesis
2D Cell Synthesis
Methodology
Major Steps
Part II
Placement Modeling: 2D Compaction
Solving the Constraints
The Sequence Pair
Sequence Pair Optimization
Move Example: Translation
Annealing: total runtime
Annealing: per-move runtime
Annealing: perfect benchmark
Annealing Solution Variance
Annealing Predictability
Part III
Transistor Chaining Theory
Chain Width Minimization
Chain Height Minimization
Methodology
Static Clustering
Clustering Example
Micro-Placement
Dynamic Transistor Chaining
Dynamic Chaining Example
Arbitrary Geometry Sharing
Geometry Sharing Demo
Datapath Cell Template
Routing Cost Model
Routing Area Insertion
Routing: Anagram-II
Compaction: Masterport
Part IV
Implementation: TEMPO
MUXFF Benchmark
Benchmarks
Benchmarks (cont.)
Benchmark Data
Tempo Runtime
Annealing Solution Variance
Predictability Data
Routing Completion Rates
Examples: dcvsl-xor4
Examples: ptl-42comp
Examples: ptl-rba
Examples: mux2-sdff
Examples: ghz-mux8-la
Part V
Contributions
Future Work
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