Table of Contents
A Quantitative Approach to Non-linear IC Process Design Rule Scaling
Overview
Process scaling
Trends
Non-linear scaling
Embedded CGaAs SRAM
PPT Slide
Cost/benefit analysis
Non-linear scaling
Area-critical design rules
Area-critical design rules
Design rule set formation
Scaling impact analysis
Performance impact analysis
Area impact analysis
Die cost estimation
Cost/benefit ratio calculation
Cost/benefit plot formation
Cost/benefit plot formation
Iterative cost/benefit analysis
Multiple iterations
PPT Slide
PUMA SRAM compiler - Stage 1
PUMA SRAM compiler - Stage 2
PUMA SRAM compiler components
Sample SRAM layout
2 k-byte test SRAM
1 k-byte embedded PUMA I-cache
PPT Slide
CGaAs area-critical design rules
CGaAs area-critical design rules
CGaAs area-critical design rules
Scaling cost estimation
Disjoint design rule sets
Incremental design rule sets
Scaling costs
Performance impact analysis
Power impact analysis
Delay impact analysis
Performance benefit
Area impact analysis
Die cost calculation
Cost/benefit - low volume
Cost/benefit - moderate volume
Cost/benefit - high volume
PPT Slide
Contributions & future work
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