PUMA_FXU Intellectual Property Core
PUMA FXU in 0.18micron bulk TSMC process
The PUMA_FXU I/P core consists of a 32-bit dual-issue 4-way superscalar
PowerPC fixed-point unit (FXU) processor that implements majority of
instructions in the PowerPC ISA and the associated verification/test environment.
The soft I/P core is available for download through UMIPS (University
of Michigan Intellectual Property Service). A detailed description
of the processor can be found here (PDF document).
Part: PUMA_FXU
Deposit Date: 01.28.04
Process Technology: TSMC 0.18micron
Type: Soft
Design: Verilog - Standard Cell
Research Advisor: Prof. Richard
B. Brown
Designer: Jayakumaran Sivagnaname and Rahul Rao
Affiliation: University of Michigan
Qualification: Pre-Silicon Verified
Instantiated: Yes
Patent: None
Description: A 32-bit dual-issue 4-way superscalar PowerPC
fixed-point unit processor that implements majority of instructions in
the PowerPC ISA.
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CREDITS
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Several individuals have contributed significantly during
the different phase of this project. The graduate students and their
contributions have been listed in chronological order with the most
recent first.
Jayakumaran Sivagnaname and Rahul Rao - Dual-Issue FXU
Design and Fabrication
Tarun Gupta - Dual-Issue Decoder Design
Alan Drake and Koushik Das - Single-Issue
FXU verilog conversion
Charles Lefurgy, James Dundas and Keith Kraver
- Puma Checker and Random Program Generator (verification environment)
Todd Basso, Alan Drake, Claude Gauthier, Spencer Gold,
Keith Kraver, Phiroze Parakh and Sean Stetson - CGaAs
and CMOS FXU Design and Fabrication.
U-M High Performance Microprocessor home page
Solid State Electronics
Laboratory
Department
of Electrical Engineering and Computer Science
University of
Michigan