Load-Store Memory and Cache Memory Subsystem*
Spencer Gold's role in the project included the design and implementation
of the load-store functional unit and the cache memory subsystem.
As a part of this effort, he designed the following chips:
0.5u CGaAs 4 KByte synchronous SRAM
0.35u CMOS non-blocking memory management unit
Optimized 0.5u CGaAs 2KByte synchronous SRAM
Our research group has produced two implementations of the PUMA microprocessor.
The first is demonstration processor designed in TSMC's 0.35 micron CMOS
process. The second was designed for Motorola's 0.5 micron CGaAs
process. These processors implement several current microarchitectural
enhancements including 3-way superscalar, superpipelined, and out-of-order
instruction execution, dynamic two-level branch prediction, and non-blocking
primary and secondary cache accesses with less than 1 million transistors.
0.35u CMOS PowerPC microprocessor
0.5u CGaAs PowerPC microprocessor
*This page created by Spencer Gold, now at Sun Microsystems