PUMA PowerPC Ultrafast Multi-Chip Architecture

Introduction

What is PUMA?

PUMA Team Members

Collaborators

PUMA Design Goal

PUMA Design Goal (cont.)

Target Process Technology

CGaAs Cross Section

CGaAs Device Parameters

Complementary Logic

Direct-Coupled FET Logic

Domino Dynamic Logic

Digital Process Improvements

Impact of CGaAs on Project

Implications of CGaAs on Architecture

PUMA Project Phases

MCM 1

MCM 1 Photo

MCM 2

MCM 2 Cross Section

MCM 3

PUMA System Diagram

Packaging Technology

Area Interconnect

PUMA ALU Test Chip

Register File Test Chip

4 KB D-Cache Test Chip

CAD Associated with PUMA

PUMA System Clocking Strategy

Negative Edge-Triggered Clocking

Clock Distribution Methods

Big-Buffer H-Tree Distribution

Buffer Tree Clock Distribution

Phase-Locked Loop Clock Distribution

CGaAs Phase-Locked Loop

CGaAs PLL Design

CGaAs PLL Block Diagram

Phase-Frequency Detector Block Diagram

Voltage-Controlled Oscillator

Divide-by-N Counter Block Diagram

CGaAs PLL Die Photo

CGaAs PLL Measured Results

Frequency vs. Voltage

CGaAs PLL: Take Two

Acknowledgments

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