As part of the ongoing research activities conducted by the High-Performance Microprocessor Project at The University of Michigan, a high speed CGaAs® 32-bit Arithmetic Logic Unit has been designed to implement the PowerPC® Instruction Set Architecture. The primary focus of this work has been to evaluate the capabilities of Domino Logic in Motorola's 0.5 µm CGaAs technology. To our knowledge, this is the first implementation of Domino Logic in a CGaAs process. The execution unit contains an adder, bi-directional shifter, logical unit, and a leading zero counter. The control unit is implemented in a mixed logic style, utilizing both DCFL and Complementary logic gates. Negative-edge triggered D flip-flops implement a single-phase clocking scheme. A segmented scan chain, consisting of a full scan chain with multiple input and output ports, ensures testability. The standard cell library, constructed using Mentor Graphics IC Station, consists of Domino, Complementary, and DCFL logic gates. The gates were sized using an optimization approach that minimized the power delay product, while balancing the rise and fall propagation delays. Cascade Design Automation's Epoch Integrated Circuit Design System provided cell compaction, floor planning, placement, and automated routing. Top level signal routing, power plane construction, LVS and DRC were performed within the IC Station framework. The chip, expected out of fabrication facilities by August 19, 1996, integrates 102,418 transistors on a 5.84 x 5.27 mm² die, contained within a 256 pin TBGA package. Based on preliminary HSPICE simulations and TACTIC timing analysis the processor is expected to operate at 617 MHz, dissipating 3.84 W from a 1.5 V power supply.