Motorola 0.50um CGaAs PowerPC Microprocessor, FXU II
Motorola 0.50um CGaAs PowerPC Microprocessor, FXU II
TSMC 0.35um CMOS PowerPC Microprocessor, FXU I
A 32-bit PowerPC superscalar microprocessor, FXU I, was designed for TSMC's 0.35 um CMOS process, and fabricated through the MOSIS VLSI Fabrication Service. The chip contains a 4KBL1-Dcache and a 1KB L1-Icache as well as a two-level branch predictor, and branch target buffer. The branch predictor is based on a 10-bit gshare scheme with a 1K-entry second-level pattern history table. Branch target addresses are stored in a direct-mapped 64-entry BTB. The superscalar execution core is comprised of a branch unit, arithmetic unit, and load/store unit. Out-of-order execution is supported by dedicated reservation stations for each functional unit and an eight-entry reorder buffer. The decode process translates complex PowerPC instructions into a series of one or more simple RISC operations, allowing a simple execution core to process complex architectural instructions. The die consists of 280 pins measures 9.9 x 9.9 mm and contains 830K transistors. The chip consumes an estimated 4 W at 50MHz and is packaged in a 391-pin ceramic PGA. The design team consisted of 6 engineers and required 37 man-months of effort. The processor is currently in the testing laboratory.
A High Speed CGaAs ALU Using Domino Logic: The execution unit of the FXU was implemented to investigate the capabilities of the CGaAs process. Simulations demonstrate that the chip is capable of operating at 617 MHz, dissipating 3.84 W from a 1.5V supply. The design has won awards in several VLSI design contests.
