MCM 1
Test vehicle
MicroModule Systems D-500 process
Includes selection of Mayo Foundation Standard Test Structures
CGaAs test Chips
Submitted to MIDAS for fabrication
MCM 1
Test vehicle
MicroModule Systems D-500 process
Includes selection of Mayo Foundation Standard Test Structures
CGaAs test Chips
Submitted to MIDAS for fabrication
Abstract :
We are designing and laying out a multichip module (MCM) which will act
as a test vehicle. It is being designed in MicroModule Systems D-500
technology and will carry six CGaAs chips which we are also designing.
The design is aimed at characterizing the MCM interconnect and
driver-receiver pairs for good signal integrity on the MCM. There will also be
some passive structures which are based on structures designed at the Mayo Foundation.
The chips we are designing are a serial to parallel (SP) and parallel to serial (PS) shift-register, and a clock generator. Two pairs of SP and PS chips (4 chips) will be driven by the clock generator at frequencies up to 1 GHz. The data will be scanned in and scanned out at a slower rate since the test equipment is limited to 400MHz. One SP chip will be used to drive an unterminated databus which will be probed at the other end. The chips will incorporate various pad driver and receiver designs which we wish to evaluate.
Clock Frequencies in VLSI systems are increasing at a rate of approximately 50% per year. However, advances in I/O techniques have not come at the same rate, and system performance is limited by the I/O bottleneck.Researchers at The University of Michigan are studying several I/O techniques for MCM's in order to determine which are best suited to the MCM environment. The Multi-Chip Module will contain four driver/receiver pairs and will run at a target clock rate of up to 1 GHz. The work is being done in the Motorola CGaAs process, and therefore the voltage swings are inherently low (on the order of 1.5V).
The circuits include variations on standard I/O techniques designed to illustrate the immediate advantage of custom designing for the MCM. These circuits include cascaded inverters, and open-drain drivers. Other circuits are more aggressive implementations which should provide insight into how far this technology can go. Current-mode circuits, as well as super-buffer fet logic circuits are currently under consideration.
MCM Designer
Chip Designers
IO Pad Design
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