Posters Displayed at ARVLSI'97

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• The PUMA FXU Architecture
  
• Hardware Design Verification for Microprocessors
  
• Improving Processor Performance by Dynamically Pre-Processing the Instruction Stream
  
• Reducing Cost of Embedded Processor via Program Compression
  
• The PUMA Multi-chip Cache Memory Hierarchy
  
• A CGaAs Multiply-Accumulate Unit
  
• Exact Algorithms for Rectangle Packing Based on the Sequence Pair
  

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