Project Summary For Fiscal Year 99

The first test circuits designed in this project were fabricated and characterized to validate circuit topologies such as DCFL, domino, and various tri-state designs in the CGaAs technology; to verify SPICE models; to evaluate different circuit designs topologies; and to demonstrate critical subcircuits. Multichip modules were also designed and tested to characterize their interconnect and to test various I/O schemes.

A CMOS version (TSMC 0.35 micron process) of the 32-bit superscalar PowerPC microprocessor was then designed to verify the architecture. The CMOS design has been fabricated and packaged, and testing is well along. (So far, no problems have been found.) The CGaAs design has also been completed, and the chips have been fabricated and packaged. They will be tested as soon as the CMOS processor testing is complete.

The processor chip, which includes an area I/O pad array (in addition to peripheral pads), will be flip-chip assembled using gold bumps on a fine-pitch MCM-L board, connecting it to level-1 cache, a memory management unit, PCI interface, and level-2 cache. The area I/O array is the densest and finest pitch array ever to be assembled on MCM-L. The remainder of this project and an accompanying AASERT will complete the system design and demonstrate the prototype in a desktop computer.

An architecture incorporating a number of advanced features, such as superscalar execution and a two-level dynamic branch predictor, was developed for small transistor budget designs. The processor implements a small on-chip primary instruction cache and a larger off-chip primary data cache. Implemented in the current 0.5-micron process, and running standard benchmark programs, the PUMA processor should achieve 0.77 instructions per cycle, and run at more than 200MHz. Other embedded processors could benefit from the PUMA studies which showed that some advanced features give a good performance return on the area and power they require, and from the efficient circuit designs in which they were implemented.

A methodology (which works for any semiconductor technology) was developed to quantitatively evaluate semiconductor processes for optimal scaling. The PUMA processor was designed in the Motorola 0.5-micron CGaAs process which had been developed by shrinking the gate length of a 0.7-micron process; it was clear that the design rules needed to be adjusted as they were scaled. As dimensions are shrunk below 0.18 micron, linear scaling will become very costly in CMOS, too. The methodology guides process engineers to scale design rules in the most cost-effective way to reach the desired objective. The heart of this method is the automated exploration of the design-rule space using a process-independent, optimizing SRAM compiler developed in this project. A cost/benefit analysis of the CGaAs design rules showed that when operating under a fixed spending cap, nonlinear scaling provides greater improvements in area and performance than linear scaling.

A gold bumping process which makes precisely-sized bumps of the desired aspect ratios has been developed in our lab as part of a flip-chip packaging scheme. Test chips having thousands of bumps with pitches as small as 50 microns are being assembled on MCMs. The processor chip includes a 315-pin area I/O pad array with a pad pitch of 6 mils, in addition to 288 pads in a staggered peripheral ring. This packaging approach is appropriate for military and aerospace applications now, and will be important for the commercial CMOS systems predicted by the SIA roadmap.

Gunning transceiver, differential voltage, and switched current I/O interfaces have been fabricated in CGaAs and tested. Test results indicate that these circuits in CGaAs can support bit rates of at least 650 Mb/s/pin (limited by the test set-up).

An advanced CGaAs transceiver based on switched-current techniques has been designed. The receiver actively terminates the input line to its characteristic impedance using an active current mirror. The transmitted current pulse is 1.5mA. The receiver is biased using a feedback circuit that overcomes process variations and power supply differences between the transmitting and receiving chips by adjusting bias levels of the receiving chip. Simulations indicate that the circuit can support 1.2 Gb/s/pin signaling while dissipating only 4.5 mW, with a 1.5 V supply. The circuits are small, so they could be implemented efficiently for high-speed chip-to-chip interfaces.

A CMOS version of the switched-current transceiver was designed, fabricated and tested. It was implemented in a 3.3 V process, but designed to operate with a 2.5 V supply, to emulate future CMOS processes which will have lower supply voltage (Vdd) to threshold voltage (Vth) ratios. This I/O link achieved a range of speeds from 880 Mb/s at 5 mW with a 2.25 V supply, to 1.05 Gb/s at 9 mW with a 3 V supply. The low power, small size, and process and voltage tolerance of this interface is exactly what is needed for future CMOS chip-to-chip communication.

A CGaAs delay-locked-loop (DLL) was designed to explore the effects of low supply voltage and headroom on phase noise performance. Simulations indicate that the DLL will operate at 500 MHz with a peak jitter of 88 ps. DLLs are important components of I/O interfaces, allowing the receiver to sync to the transmitter clock.

A CGaAs PLL clock generator which operates at up to 800 MHz with a 1.5 V supply and 120 ps phase jitter was designed and tested. The CGaAs design was operational at a supply voltage as low as 0.8 V. Step-up clock generators such as this are important components of modern microprocessor systems.

An accurate phase jitter simulation method, which includes the phase jitter model in transient simulations, has been developed. This tool can be used to analyze circuits for phase jitter, allowing the designer to optimize them in this important parameter.

A low-noise PLL clock generator, employing current-steering logic, was designed, fabricated and tested in a 0.5-micron, 3.3 V CMOS process. This design, which benefited from availability of the jitter simulator, was also done for a lower power supply voltage to study and develop low-headroom circuits. Measured results show a top frequency of nearly 800 MHz with a power supply voltage of 1.8 V. It achieves a measured absolute phase jitter of less than 60 ps, and an RMS cycle-to-cycle phase jitter of 10 ps. This is the best phase jitter performance of any published PLL, and it was achieved with low-voltage techniques which will have direct applicability to future CMOS circuits.

A transistor-level micro-placement tool called TEMPO was developed for two-dimensional leaf cell synthesis. It generates custom-quality layouts for such high-performance logic families as cascode voltage switch logic, pass transistor logic, and domino CMOS. This is achieved through powerful transformations such as dynamic geometry sharing through transistor chaining and arbitrary geometry merging. TEMPO enables the quick migration of cell libraries to new fabrication processes.

A constructive logic synthesis tool named M31 interleaves the traditionally separate technology-independent logic restructuring and technology-dependent library binding stages. M31 is based on Boolean decomposition strategy that ties together the structural properties of the functions being synthesized, the structural attributes of the implementation network, and the functional content of the target library. The resulting implementations are consistently smaller and faster than those generated using conventional logic synthesis. In addition, they can be incrementally modified to create variants that achieve other area/speed trade-offs.

A methodology and tools have been developed for minimizing the effects of capacitively-coupled crosstalk. By using an accurate and consistent empirical model for wiring resources and constraints, the tool has made coupled noise and delay predictable, and thus avoidable. A congestion-driven placement algorithm was developed to help minimize the incidence of capacitive coupling, and a global route-embedder was developed to guide the detailed router to meet timing and noise constraints.

The packaging technology based on gold bumps will be demonstrated with test chips on MCM substrates. These parts are being assembled, and will be tested to evaluate yield vs. bump pitch, bump aspect ratio, and number of bumps.

And finally, an MCM-L based system is being designed with the CGaAS FXU, CMOS cache, and an FPGA-based memory management system and PCI interface. This work will be completed under a related AASERT project.

We have worked with Todd Weatherford at the Naval Postgraduate School (408-656-3044) on radiation hardness issues. We are collaborating with 3-M on flip-chip assembly and with Multek on MCM-L technology. We have also worked with SPEC (Garry McMillan, 512-306-1100), sharing the costs of wafers, masks and packaging for CGaAs runs. We have collaborated with Capt. Gerald J. Trombley at the National Security Agency, and visited with people from Wright Laboratory (Dr. Charles L. A. Cerny) and Phillips Laboratory (Capt. Kenneth G. Merkel) about CGaAs technology and circuits.