PUMA Register File*

A 64 X 32 bit general purpose register file with 2 read ports and 1 write port is being designed to operate in the PUMA's FPU.

The 1st prototype will be implemented in a .5 micron complementary GaAs process designed by Motorola. It will utilize a 1 GHz single-phase clock and a 1.5 V power supply. The register file will have a 0.62 ns access time.

The design will be ready for tape out in January, 1996 and will be fabricated by May, 1996.

  • Postscript Version of Paper Prepared for Mentor Graphics Contest (2nd Place)
    *Page designed by Claude Gauthier, now at Sun Microsystems