by
Eric Hao
GSRA
University of Michigan
Abstract: To achieve higher levels of performance, processors are being built with wider issue widths and larger numbers of functional units. In the past ten years, instruction issue width has grown from one (MIPS R2000, Sun MicroSparc, Motorola 68020), to two (Intel Pentium, Alpha 21064) to four (MIPS R10000, Sun UltraSparc, Alpha 21164, PowerPC 604). This increase in issue width will continue as processors attempt to exploit even higher levels of instruction level parallelism. However, to effectively exploit the performance potential of such processors, instruction fetch rate must also be increased. In addition, the increase in hardware complexity for implementing such processors must be minimized so that such processors can be implemented with a competitive cycle time.
Block-structured ISAs are a new class of instruction set architectures that were designed to address the performance obstacles faced by processors attempting to exploit high levels of instruction level parallelism. The major distinguishing feature of a block-structured ISA is that it defines the architectural atomic unit (i.e. the instruction) to be a group of operations. These groups of operations are called atomic blocks. This redefinition of the atomic unit enables the block-structured ISA to simplify many implementation issues for wide-issue processors. Block-structured ISAs can also increase the instruction fetch rate of a processor through the use of an optimization called block enlargement. Block enlargement combines separate atomic blocks into a single atomic block, increasing the amount of work that can be fetched each cycle by the processor.
This talk will present an overview of block-structured ISAs, describing its performance advantages over traditional ISAs. It will describe the reductions in hardware complexity enabled by block-structured ISAs and the block enlargement optimization. This talk will also present simulation results comparing the performance of a processor implementing a block-structured ISA to that of a processor implementing a conventional ISA.