Marios C. Papaefthymiou - GHz-Class Charge-Recovery Research


This page is under construction. The following papers describe recent work by Marios and his students on charge recovery design for GHz clock rates.

V. Sathe, J. Kao, and M. C. Papaefthymiou. Resonant-clock latch-based design. JSSC, Vol. 43, No. 4, April 2008.

V. Sathe, J. Kao, and M. C. Papaefthymiou. A 0.8GHz - 1.2GHz single-phase resonant-clocked FIR filter with level-sensitive latches. CICC, September 2007.

V. Sathe, J. Kao, and M. C. Papaefthymiou. RF2: A 1GHz filter with distributed resonant clock generator. Symposium VLSI Circuits, June 2007.

V. Sathe, J.-Y. Chueh, and M. C. Papaefthymiou. Energy-efficient GHz-class charge-recovery logic. JSSC, Vol. 42, No. 1, January 2007.

J.-Y. Chueh, V. Sathe, and M. C. Papaefthymiou. 900MHz to 1.2GHz two-phase resonant-clock network with programmable driver and loading. CICC, September 2006.

V. Sathe, J.-Y. Chueh, and M. C. Papaefthymiou. A 1.1GHz charge-recovery logic. ISSCC, February 2006.