RESEARCH BRIEFS

Research Briefs by Faculty

Todd Austin
Peter M. Chen
Edward S. Davidson
Stephen W. Director
John P. Hayes
Trevor Mudge
Marios Papaefthymiou
Steven K. Reinhardt
Karem A. Sakallah
Gary S. Tyson

Research Briefs by Subject

Architecture

  1. Attaining higher performance with a Trace Cache and Fill Unit
  2. Architecture and Operating Systems Interactions
  3. The Bi-Mode Branch Predictor
  4. Block-Structured Instruction Set Architectures
  5. Branch Prediction
  6. Communication Characterization of a Cray T3D
  7. Design and Testing of VLSI-Based Systems
  8. Early Design Cycle Timing Simulation of Caches
  9. Evaluation of Compiler Optimization Techniques for HPS
  10. Goal-Directed Performance Tuning for Scientific Applications
  11. Hardware Design Verification for Microprocessor s
  12. HPS -- Microarchitecture for High Performance Computing Engines
  13. Improving processor performance by dynamically pre-executing instructions under cache misses
  14. Instruction Prefetching Using Branch Prediction Information
  15. An Instruction Stream Compression Technique
  16. Limits of Branch Predictability
  17. Memory System Hierarchies for High Speed Microprocessors
  18. MIRV: The Michigan Intermediate Representation Format
  19. Modulo Scheduling, Machine Representations, and Register-Sensitive Algorithms
  20. Out of Order Issue
  21. Performance Aspects of Multi-Lateral Cache Organizations for Single-Chip Processors
  22. Reducing Communication Cost in Directory-Based Cache Coherent Systems
  23. Rio: High-Performance File Systems via Reliable Memories
  24. A Unified Approach to Parallel Performance Tuning for Irregular Applications

Computer Aided Design

  1. Algorithmic Layout Optimization of CMOS Cells
  2. Algorithmic Techniques for Custom-Quality Layout Cell Generators
  3. Architectural CAD
  4. Design and Testing of VLSI-Based Systems
  5. Hardware Design Verification
  6. Hardware Design Verification for Microprocessors
  7. High-Level Modeling of Timing Constraints
  8. High-Level Timing Analysis
  9. Structural Logic Synthesis
  10. Switching Noise Containment in Printed Circuit Boards
  11. Symbolic Analysis of Digital Circuit Dynamics
  12. Timing analysis of dynamic logic
  13. Uniform Timing Models for Logic Gates and Interconnect Structures in High-Speed Digital Systems