John P. Hayes
Students: H. Al-Asaad, S. Raasch, D. Van Campenhout
Professors: John Hayes, T. Mudge, R. Brown
Sponsor: DARPA
The goal of this project is to develop and evaluate a practical hardware design verification methodology and supporting CAD tools for high-performance microprocessors. The approach being taken has two major features: the synthesis of models for actual design errors, and the adaptation of test technology for physical faults to detect these errors. The PUMA high-performance microprocessor design project currently under way at Michigan serves as a major experimental test-bed and demonstration system for the verification research. A comprehensive database is being constructed of the actual design errors encountered in this and related projects. Systematic means of simulating (modeling), detecting, and correcting these errors are under investigation. The Verilog hardware description is used to represent the target designs and their design errors. A high-level (functional) methodology is being developed to construct simulation models and detection methods for design errors. Verification tests are obtained via techniques borrowed from physical fault testing, which exploit recent results in MichiganUs research into high-level, model-based testing methods. This approach offers several advantages over alternative methods: the error models are derived directly from real design errors; unlike most formal verification methods, specification errors can be detected; it has good computational efficiency due to its high-level, functional nature; it has the ability to provide provably complete coverage of targeted errors; it can deal directly with hard cases, a key requirement for highly reliable systems; and finally, it is compatible with existing HDL-based design methodologies and CAD tools.
Students: A. Chowdhary, H. Kim
Professor: John Hayes
Sponsor: National Science Foundation
The objectives of this research are to develop efficient test generation techniques and design methods to both enhance the testability and reduce the costs of circuits employing very-large-scale integration (VLSI). A major theme of our work is the use of high-level methods that exploit the hierarchical structure and functional behavior of VLSI-based systems. In testing, the goal is to develop automatic test-pattern generation and design-for-testing methods that are orders of magnitude more efficient than conventional approaches which are based on low, gate-level models. We are also studying ways to enable complex integrated circuits to test themselves by the introduction of built-in-self test (BIST). Finally, we are developing novel techniques for mapping logic circuits into field-programmable gate arrays (FPGAs) using an approach based on integer linear programming.
Students: H. Yalcin
Professor: John Hayes
Sponsor: Semiconductor Research Corp.
This is a task within a larger research effort at Michigan aimed at developing practical approaches and CAD tools for timing analysis of VLSI circuits at multiple levels of abstraction, including the gate, register, and processor levels. This particular project is concerned with ways to represent, analyze, and simulate the timing behavior of hierarchical logic circuits. A key requirement is the ability to trade off accuracy for computational ease of use in quantifiable waysQwe want to achieve the computational efficiency allowed by high-level models, along with the accuracy inherent in low-level approaches. A basic theme is the separation of timing from the functional aspects of circuit behavior, so that the timing can be dealt with directly. We are presently studying timing problems that are common to several levels, such as determining the sensitization conditions required to produce specific path delays, as well as problems that are unique to the high level.
Students: A. Gupta
Professor: John Hayes
Sponsor: Intel Corp.
This project aims to develop synthesis techniques for automatically generating the physical layout of CMOS cells and cell-based VLSI circuits such as microprocessors. It focuses on algorithmic synthesis of both static and dynamic cells subject to area and delay constraints, with the achievement of minimal or near-minimal layout area as the major goal. The specific topics being addressed include: synthesis of complex CMOS cells using one and two-dimensional layout styles; synthesis of circuits composed of complex cells; subcircuit reordering and transistor resizing techniques to minimize area; performance-driven cell synthesis; and the integration of the synthesis techniques that are developed into a general CAD-tool environment.