JOHN P. HAYES

Education

• Ph.D. (Electrical Engineering), University of Illinois, Urbana, 1970
  
• M.S. (Electrical Engineering), University of Illinois, Urbana, 1967
  
• B.E. (Electrical Engineering), National University of Ireland, Dublin, 1965

Employment

• Shell Benelux Computing Centre, The Hague, Systems Engineer, 1970-72
  
• University of Southern California, Depts. of Electrical Enginering-Systems and Computer Science, Asst. Professor 1972-77, Assoc. Professor, 1977-82
  
• Stanford University, Visting Assoc. Professor, 1979
  
• McGill University and Universite de Montreal, Visiting Professor, 1988
  
• LogicVision Inc., San Jose, CA, Visiting Researcher, 1997
  
• University of Michigan, Ann Arbor, Dept. of Electrical Engineering and Computer Science, Professor, 1982-present

Honors and Awards

• USC Engineering Faculty Service Award, 1982
• IEEE Fellow, 1985
• Best Paper Award, IEEE Micro, 1986
• Best Paper Award Supercomputing'90 Conference
• Research Excellence Award, EECS Department, 1990
• Service Excellence Award, EECS Department, 1992
• EDS Distinguished Speaker, SUNY Buffalo, 1995
• Best Paper Award: 10th Conf. on VLSI Design, 1997
• Distinguished Faculty Achievement Award, 1999

Research Activities

Computer aided design (CAD): testing, design verification, and synthesis. Computer architecture: fault-tolerant and safety-critical systems. VLSI design: automated cell synthesis and embedded systems-on-a-chip.

Recent Publications

• R. L. Maziasz and J. P. Hayes, "Layout Minimization of CMOS Cells", Kluwer Academic Publishers, Boston, 1992.

• J. P. Hayes, "Computer Architecture and Organization," Third Edition, McGraw-Hill, New York, 1998.

• B. T. Murray and J. P. Hayes, "Testing ICs: getting to the core of the problem," IEEE Computer, vol. 29, no. 11, pp. 32-38, Nov. 1996.

• H.-K. Ku and J. P. Hayes, "Systematic design of fault-tolerant multiprocessors with shared buses," IEEE Transactions on Computers, vol. 46, pp. 439-455, April 1997.

• H. Yalcin and J. P. Hayes, "Event propagation conditions in circuit delay computation," ACM Transactions on Design Automation of Electronic Systems, vol. 2, pp. 249-280, July 1997.

• H. Al-Asaad, B. T. Murray, and J. P. Hayes, "On-line BIST for embedded systems," IEEE Design and Test, vol. 15, no. 4, pp.17-24, Oct.-Dec. 1998.

• H. Kim and J. P. Hayes, "High-coverage ATPG for datapath circuits with unimplemented blocks," Proc. 1998 Intl. Test Conf., Washington, DC, pp. 577-586, Oct. 1998.

• A. Gupta and J. P. Hayes, " Optimal 2-D cell layout with integrated transistor folding," Proc. Int'l Conf. on Computer-Aided Design (ICCAD 98), San Jose, Calif., pp. 128-135, Nov. 1998.

• K. Chakrabarty, B. T. Murray, and J. P. Hayes, "Optimal zero-aliasing space compaction for test responses," IEEE Transactions on Computers, vol. 47, pp. 1171-1187, Nov. 1988.

• D. Van Campenhout, H. Al-Asaad, J. P. Hayes, T. Mudge, and R. B. Brown, "High-level design verification of microprocessor via error modeling," ACM Transactions on Design Automation of Electronic Systems, vol. 4, 1999.