KAREM A. SAKALLAH
Education
- Ph.D. (Electrical Engineering), Carnegie Mellon University, 1981
- M.S.E.E. (Electrical Engineering), Carnegie Mellon University, 1977
- B.E. (Electrical Engineering), American university of Beirut, 1975
Employement
- Ministry of Electricity and Water, Dept. of Network Design, Kuwait, 1975-1976
- CMU and Westinghouse Electric Corp., Ocean Thermal Energy Conversion Project, 1977-1978
- CMU, Army Electronics Command and Naval Research Laboratory, Summers 1977-1979
- Carnegie-Mellon University, Dept. of Electrical Engineering, Visiting Assistant Professor, 1981-1982
- Digital Equipment Corporation, Semiconductor Engineering Group/Computer Aided Design Dept.
- Principal Software Engineering, 1982-1988
- University of Michigan, Ann Arbor, Dept. of Electrical Engineering and Computer Science, Associate Professor, 1988-present
Research Interests
VLSI, computer-aided design, timing verification, optimal clocking.
Recent Publications
- M. A. Riepe, J. P. M. Silva, K. A. Sakallah and R. B. Brown, "Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, no. 1, pp. 113-129, March 1996.
- C.-H. Chang, E. S. Davidson and K. A. Sakallah, "Maximum Rate Single-Phase Clocking of a Closed Pipeline including Wave Pipelining, Stoppability, and Startability," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 12, pp. 1526-1545, December 1995.
- T. M. Burks, K. A. Sakallah and T. N. Mudge, "Critical Paths in Circuits with Level-Sensitive Latches," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, no. 2, pp. 273-291, June 1995.
- A. I. Kayssi and K. A. Sakallah, "Timing Models for Gallium Arsenide Direct-Coupled FET Logic Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 3, pp. 384-393, March 1995.
- A. I. Kayssi and K. A. Sakallah, "Delay Macromodels for Point-to-Point MCM Interconnections," IEEE Transactions on Components, Packaging and Manufacturing Technology-Part B, vol. 17, no. 2, pp. 147-152, May 1994.
- K. A. Sakallah, T. N. Mudge, T. M. Burks and E. S. Davidson, "Synchronization of Pipelines," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 8, pp. 1132-1146, August 1993.
- A. I. Kayssi, K. A. Sakallah and T. N. Mudge, "The Impact of Signal Transition Time on Path Delay Computation," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 40, no. 5, pp. 302-309, May 1993.
- A. I. Kayssi and K. A. Sakallah, "Macromodeling and Simulation of RC Interconnection Circuits," in Proceedings, First LAAS International Conference on Computer Simulation (ICCS'95), September 1995, Beirut, Lebanon.
- J.-G. Yook, V. Chandramouli, L. P. Katehi and K. A. Sakallah, "Computation of Switching Noise in PCBs for Digital Packages," in Proceedings, 4th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP'95), October 1995, Portland, Oregon. (accepted)
- A. Chandna, D. C. Kibler, R. B. Brown, M. Roberts, and K. A. Sakallah, "The Aurora RAM Compiler," in Proceedings, IEEE/ACM Design Automation Conference (DAC), pp. 261-266, June 1995, San Francisco, California.
- T. M. Burks and K. A. Sakallah, "Optimization of Critical Paths in Circuits with Level-Sensitive Latches," in Digest of IEEE International Conference on Computer-Aided Design (ICCAD), pp. 468-473, November 1994, San Jose, California.
- J. P. M. Silva and K. A. Sakallah, "Dynamic Search-Space Pruning Techniques in Path Sensitization," in Proceedings, IEEE/ACM Design Automation Conference (DAC), pp. 705-711, June 1994, San Diego, California (nominated for best paper award).
- A. I. Kayssi and K. A. Sakallah, "Macromodel Simplification Using Dimensional Analysis," in Proceedings, IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 335-338, June 1994, London, England.
- J. P. M. Silva and K. A. Sakallah, "Efficient and Robust Test Generation-Based Timing Analysis," in Proceedings, IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 303-306, June 1994, London, England.