Marios C. Papaefthymiou - Research Summary
Marios' research interests are in energy-efficient high-performance computer systems. Currently, the main thrust of his research group is on ultra-low-power charge-recovering (a.k.a. energy-recovering or adiabatic) circuits and VLSI architectures for mobile communicators, portable computers, and bio-embedded networks. Another area of active research is design automation algorithms and tools for managing design complexity, focusing on fast power estimators and geometric partitioners.
Over the past few years, Marios' group has spearheaded the exploration of practical charge-recovery technologies that can be used with mainstream design flows. Several advances have been demonstrated via working silicon prototypes, including the first-ever GHz-class charge-recovery ASICs and logic families, a resonant clocking technology that is compatible with standard ASIC design flows, and the first charge-recovery circuit family that operates using a single-phase power-clock waveform. Using this circuit family, Suhwan Kim and Conrad Ziesler designed a multiplier chip that received First Prize in the VLSI Design Contest (Operational Category) of the 2001 ACM/IEEE Design Automation Conference.
Before venturing into low-energy design, Marios worked extensively in the area of timing analysis and optimization. His investigation focused on the retiming transformation, resulting in several asymptotically efficient retiming algorithms for edge-triggered and level-clocked circuits under general delay models that account for setup times, hold times, register delays, and clock skew.
Support for Marios' research group is provided by National Science Foundation, ARO, DARPA, SRC, IBM Corporation, and an equipment grant from Intel Corporation.