MARIO PAPAEFTHYMIOU

Education

• Ph.D., Massachusetts Institute of Technology, 1993
• M.S., Massachusetts Institute of Technology, 1990
• B.S., California Institute of Technology, 1988

Employment

• University of Michigan, Ann Arbor, Department of Electrical Engineering and Computer Science, Asssitant Professor, September 1996 - present
• Yale University, Dept. of Electrical Engineering and Computer Science, Assistant Professor, July 1993 - August 1996.

Honors and Awards

• Arthur Greer Memorial Prize for research and teaching in computer systems, Yale College, June 1996
• NSF Career Development Award, February 1996
• Best Paper Award, 32nd ACM/IEEE Design Automation Conference, June 1995
• ARO Young Investigator Award, February 1995

Research Interests

VLSI, Computer-aided design, design and analysis of algorithms, parallel and distributed computing.

Recent Publications

• M. C. Papaefthymiou, "Asymptotically efficient retiming under setup and hold constraints," In Technical Digest of Papers of the 1998 IEEE/ACM International Conference on Computer-Aided Design, November 1998.

• M. C. Papaefthymiou, E. G. Friedman, and X. Liu, "Retiming and clock scheduling for high-performance synchronous circuits," In PATMOS '98, Eighth International Workshop on Power and Timing Modeling, Optimization and Simulation, October 1998.

• S. Kim and M. C. Papaefthymiou, "True single-phase energy-recovering logic for low-power, high-speed VLSI," In International Symposium on Low-Power Electronics and Design, August 1998.

• F. Wang, M. C. Papaefthymiou, and M. S. Squillante, "Performance evaluation of gang scheduling for parallel and distributed multiprogramming," In Workshop on Job Scheduling Strategies for Parallel Processing of the 1997 International Parallel Processing Symposium, April 1997.

• A.T. Ishii, C.E. Leiserson, and M.C. Papaefthymiou, "Optimizing Two-Phase, Level-Clocked Circuitry," Journal of the Association for Computing Machinery, January 1997.

• M.S. Squillante, F. Wang, and M.C. Papaefthymiou, "Stochastic Analysis of Gang Scheduling in Parallel and Distributed Systems," Performance Evaluation, 27&28:273-296, 1996.

• K.N. Lalgudi and M. Papaefthymiou, "Fixed-Phase Retiming for Low Power Design," In 1996 International Symposium on Low Power Electronics and Design, August 1996.

• M.S. Squillante, F. Wang, and M.C. Papaefthymiou, "An Analysis of Gang Scheduling for Multiprogrammed Parallel Computing Environments," In Proceedings of the 8th ACM Symposium on Parallel Algorithms and Architectures, June 1996.

• K.N. Lalgudi M.C. Papaefthymiou, and M. Potkonjak, "Optimizing Systems for Effective Block-Processing: The $k$-Delay Problem," In Proceedings of the 33rd ACM/IEEE Design Automation Conference, June 1996.

• M. Knapp, P. Kindlmann, and M.C. Papaefthymiou, "Implementing and Evaluating Adiabatic Arithmetic Units," In IEEE 1996 Custom Integrated Circuits Conference, May 1996.

• F. Wang, H. Franke, M.C. Papaefthymiou, P. Pattnaik, L. Rudolph, and M.S. Squillante, "A Gang Scheduling Design for Multiprogrammed Parallel Computing Environments," In Workshop on Job Scheduling Strategies for Parallel Processing} held in conjunction with the International Parallel Processing Symposium, April 1996.

• A.T. Ishii and M.C. Papaefthymiou. "Efficient Pipelining of Level-Clocked Circuits with Min-Max Propagation Delays," In TAU'95 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, November 1995.

• K.N. Lalgudi and M.C. Papaefthymiou, "Delay: An Efficient Tool for Retiming with Realistic Delay Modeling," In Proceedings of the 32nd ACM/IEEE Design Automation Conference, June 1995. Received Best Paper Award.

• K.N. Lalgudi and M.C. Papaefthymiou, "Efficient Retiming under a General Delay Model," In Advanced Research in VLSI: Proceedings of the 1995 Chapel Hill Conference, March 1995.

• M.C. Papaefthymiou, "Understanding Retiming through Maximum Average-Delay Cycles," Mathematical Systems Theory, No. 27, pp. 65-84, 1994.

• M.C. Papaefthymiou and J. Rodrigue, "Implementing Parallel Shortest-Paths Algorithms," In The Third DIMACS International Algorithm Implementation Challenge on Parallel Algorithms, October 1994.

• M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M.C. Papaefthymiou. "Precomputation-Based Sequential Logic Optimization for Low Power," IEEE Transactions on VLSI Systems, Special Issue on Low Power Design, December 1994.

• M.C. Papaefthymiou and K.H. Randall, "Tim: A Timing Package for Two-Phase, Level-Clocked Circuitry," In Proceedings of the 30th ACM/IEEE Design Automation Conference, June 1993.

• M.C. Papaefthymiou and K.H. Randall, "Edge-Triggering vs. Two-Phase Level-Clocking," with K.H. Randall. In Research on Integrated Systems: Proceedings of the 1993 Symposium, March 1993.