GARY S. TYSON

Education

• Ph.D. (Computer Science), University of California, Davis, 1997
• M.S. (Computer Science), California State University, Sacramento, 1988
• B.S. (Computer Science), California State University, Sacramento, 1986

Employement

• Assistant Professor, EECS, University of Michigan, Ann Arbor, 1997 - present
• Assistant professor, CS, University of California, Riverside, 1995-96
• Research Assistant, CS, University of California, Davis, 1994-95
• Associate Instructor, CS, University of California, Davis, 1993-94
• Graduate Research Assistant, CS, University of California, Davis, 1992-93
• Lecturer, CS, California State University, Sacramento, 1988-91

Honors and Awards

• Keynote Speaker, 9th International Symposium of System Synthesis, IEEE, 1996
• Best Presentation Award, 28th Annual Symposium on Microarchitecture, 1995
• Best Presentation Award, 26th Annual Symposium on Microarchitecture, 1993
• University of California Regents Fellowship, 1992-93
• Member, IEEE, ACM

Research Interests

Computer architecture, compiler design, interface specification between code optimization and instruction set design, memory systems

Recent Publications

• "Managing Data Caches using Selective Cache Line Replacement," International Journal of Parallel Programming, Vol. 25 No. 3, 1997.

• "Evaluating the Effects of Predicated Execution on Branch Prediction," International Journal of Parallel Programming, Vol. 24 No. 2, 1996.

• "A New Approach to Cache Management," Proceeding of the 28th Annual Symposium on Microarchitecure, Nov 28 - Dec 1, 1995.

• "The Effects of Predicted Execution on Branch Prediction," Proceeding of the 27th Annual Symposium on Microarchitecure, Nov 30 - Dec 2, 1994.

• "Code Scheduling for Multiple Instruction Stream Architectures," International Journal of Parallel Programming, Vol. 22 No. 3, 1994.

• "A Study of Single-Chip Processor/Cache Organizations," Proceeding of the 21st Annual Symposium on Computer Architecture, Apr. 18-21, 1994

• "Techniques for Extracting Instruction Level Parallelism on MIMD Machines," Proceeding of the 26th Annual Symposium on Microarchitecure, Dec. 1-3, 1993.

• "An Interactive Compiler Development System," First Tcl/Tk Workshop, June 10-11, 1993.

• "Modifying VM Hardware to Reduce Address Pin Requirements," Proceeding of the 25th Annual Symposium on Microarchitecure, Dec. 1-4, 1992.

• "MISC: A Multiple Instruction Stream Computer," Proceeding of the 25th Annual Symposium on Microarchitecure, Dec. 1-4, 1992.

• "A Partitioned TLB Approach to Reduced Address Bandwidth," Proceeding of the 19th Annual Symposium on Computer Architecture, May 19-21, 1992