Group Assignment 3 -- EECS 270, Fall '09

Due Monday, Nov 9th @2:00pm in box.


Name: _______________________________ unique name: ________________

Name: _______________________________ unique name: ________________

Name: _______________________________ unique name: ________________

You are to turn in this sheet as a cover page for your assignment. This is a group assignment, all of the work should be that of only your group members. Assignments that are unstapled, lack a cover sheet, or are difficult to read will lose at least 50% of the possible points and we may not grade them at all.

It is expected that each group member contributed to the assignment; non-contributing members should not have their name on this document. This assignment is worth about 1% of your grade in the class and is graded out of 30 points.


  1. Consider the following state diagram:
    Do the following [10 points]
    1. Create the transition and state/output tables for this state diagram.
    2. Write the transition equation and output equation. Try to minimize the logic used.
    3. Draw the circuit which implements this.
  2. Problem 5.11 from the text. [10 points]
  3. For this problem you will be designing a serial comparator. This device will take two numbers as input, with one bit of each number being provided each cycle (least significant bit first). It is then to figure which value is the greater one. More formally:
    The machine has three inputs (X, Y and reset) and one output (Z) in addition to the clock. If the reset input is a 1, the output should be 0, otherwise the output will be determined by X and Y. The X and Y inputs are binary numbers given one bit at a time with the least significant bit given first and are valid on the rising edge of the clock (as well as well before and after that edge.) The output Z is to be 1 if the bits of X seen so far is larger (as a binary number) than the bits of Y seen so far (since reset last went low). Consider the sample input and output sequence below (note: the rightmost bits are the oldest!):

    In this figure first X and Y are both zero, so X is not greater than Y and therefore Z=0. On the next rising edge of the clock X is now 1 (for a running value of 10) and Y is 0 (for a running value of 00) so the running value of X is greater than the running value of Y and therefore Z=1.

    Design a circuit which implements the above. You may use only standard gates, MUXes, decoders, encoders, and D flip-flops. You must clearly show your work. [10 points]