counterv

Counter and Shift Register Examples

module counter(clock, reset, count);
    input clock, reset;
    output [3:0] count;

    reg [3:0] next_count,count;

    always@*
    begin
        if(count<15)
            next_count=count+4'd1;
        else
            next_count=count;
        end

        always@(posedge clock)
        begin
        if(reset)
            count<=4'd0;
        else
            count<=next_count;
        end
endmodule

You do not need to use a module as shown above. You can simply put the following Verilog in with your traffic controller FSM
and use the variable count and counter_reset as though they are "global".

reg [3:0] count;
reg counter_reset;

always@(posedge clock)
begin
if (counter_reset) count <= 0;
else count <= count +1;
end

Here is a simple 8 bit shift register example. Data on serial_in is shifted into the register shiftreg on each rising edge of clk. The braket notation means to concantenate the two
quantities shiftgreg[6:0] and serial_in.

reg [7:0] shiftreg;
always@ (posedge clk)
begin
    shiftreg <= {shiftreg[6:0], serial_in};

end