EECS 270: Lab 2

Overview

Preparation

• See section 2.10, page 85 of Vahid for a discussion on propagation delay.
• See section 4.3 of Vahid for half, full and binary ripple carry adder operation. We will use the binary carry adder to demonstrate the effects of propagation delay on adder operation.

Design Specification

Figure 1: 5-input XOR

Figure 2: 4-bit adder

You will be creating two different Quartus projects, one for the five-input XOR, and one with the ripple-carry adder. You will then examine the propagation delay of the circuit using both a simple abstract model and then using the Quartus tools to provide a "real" model of the FPGA delay. For the 5-input XOR gate you are to use switches SW0-SW4 (in any order) as your inputs and LEDR[0] as the output.

For the adder SW[3:0] will be "A[3:0]" (in that order), SW[7:4] will B[3:0] (again in that order) and Cin will be KEY3 (recall that the KEY inputs are active low). KEY3 will apply a logical 1 when it is not pushed and a logical low when it is pushed. Your outputs will have S[3:0] mapped to LEDR[3:0] and Cout mapped to LEDG[7].

Implementation details
The 5-input XOR gate should be straightforward to implement. The XOR gates needed are found on the symbol tool under "primitives → logic". The ripple-carry adder requires you to learn a few more things about the Quartus tools, so we will step you through it.

Don't forget to save the project early and often!

Once you've finished copying the 5-input XOR design, you will need to do the following to get the 4-bit adder working:

1. First, don't forget you want to to start a new Quartus project when doing the ripple-carry adder. That is, the adder and the 5-input XOR should be different projects (and ideally different directories). Call the new project (as well as the top-level module) four_bit_adder.
2. Once you've created a new project for the adder, the first thing you should do is create a schematic as shown in Figure 3. Be sure to name everything the same as we did (though don't worry about instance numbers).
   Figure 3: Full-adder
   
3. Save the schematic as "full_adder.bdf" (not four_bit_adder).
4. Now select "File → Create/Update → Create Symbol files for the current file".
   
5. You will get a message asking you to verify the file, followed by a successful completion message.
   
6. Now open a new schematic and name it the same as what you named your top module (You named it four_bit_adder per the above directions, right?). That should be the default when you try to save it.
7. When you open the symbol tool, a new option appears "Project". See Figure 4. Select "Project → full_adder" from the symbol tool menu and place the full-adder in your schematic.
   
   Figure 4: New option in the symbol tool.
   
8. This would be a good time to save!
9. Now the full-adder symbol probably doesn't have the inputs and outputs in the same order as they are in Figure 2. So what you need to do right-click on the full_adder symbol and select "Edit Selected Symbol".
10. You should find that by grabbing the wires (not the text!) with the mouse, you can change the order of the signals. Make it match what you see in Figure 2 (Cin on the top left, then A then B. On the right you have S on the top then Cout.) Try to keep the spacing about the same as it was.
11. Save the file (use the default name which should full_adder.bsf) then close the file ("File → Close").
12. Again, this would be a good time to save.
13. Now back in the top-level file you will notice that the order of the adder's inputs and outputs haven't changed. Select the adder, right click on it, and then choose "Update symbol or block". That pops up a window asking what you want to update. In this case it doesn't matter which of the options you select (the default is fine).
14. Now all you need to do is complete the connections to make your figure look like Figure 2. Be sure to name everything correctly!

Design Notes and Hints

1. Don't forget to save often. Especially when playing with the schematic editor, the software will occasionally crash.
2. When you want to run wires from one place to another, you can't generally just drag the wires from start to finish and expect it to look good. You will often need to draw the wire "part way" and then start it from there.
3. Functional Simulation: A functional simulation does not model any delay (propagation delay) through the logic circuit. The outputs change instantaneously with the inputs. To set ModelSim for functional simulation, under Assignments → Settings EDA Tool Settings → Simulation → More EDA Netlist Writer Settings set "Generate netlist for functional simulation only" to ON.
4. Timing Simulation: A timing simulation models the delays through the various logic gates. The output will not change instantaneously with the inputs. To set ModelSim for timing simulation, under Assignments → Settings EDA Tool Settings → Simulation → More EDA Netlist Writer Settings set "Generate netlist for functional simulation only" to OFF.
   

Deliverables

1. Pre-Lab (30 points) 
   

2. In-Lab (15 points)
   

3. Post-Lab (30 points)
   

We will use ModelSim to find the maximum propagation delay of the XOR and the 4 bit carry adder circuits. The maximum propagation delay is the longest time it takes an output to change after a change in the input. Test scenarios to do this are provided for you for each circuit. To measure the delay, you will need to use Modelsim as you did before, but set "Generate netlist for functional simulation only" to OFF (see the Design Notes and Hints). In timing simulation mode, ModelSim will model actual delays on the FPGA.

When running a timing simulation, you will be prompted to choose a timing model. If you do not receive this prompt, you are running a functional simulation, not a timing simulation. The Fast Model runs the simulation using the FPGA's best-case timing delays, and the Slow Model uses the FPGA's worst-case timing delays. If your design works correctly in a Slow Model timing simulation, it is an almost certain indication that the design will work correctly on the actual hardware as well. Therefore, for this lab, and in all future timing simulations in this course, you should use the Slow Model. With the slow model, you will also have to choose either the Slow -7 1.2V 85 Model or Slow -7 1.2V 0 Model. Choose the Slow -7 1.2V 85 Model.

Use your functional testbench model from lab 1 as a starting point. Waiting 40ns after the input change should be long enough to observe the output delay. You can set up two cursors to measure delay with ModelSim. To get the second cursor, click on the yellow + button in the lower right corner of the waveform display in signal window. The entire simulation (0 to 80ns) should be displayed, with the names of the inputs and outputs clearly visible.

1) Produce the XOR  timing simulation for following test case. Use the cursors to show the worst case delay from the input change to the output. Measure the time from V going from  0-->1 to OUT going 0-->1 (10 points)


V W X Y Z
0  0  0  0  0 
wait 40ns
1  0  0  0  0
wait 40ns