EECS 270: Calculator Lab 

Overview

Preparation

• Read the example found at the end of this lab about how to use MUXes to design a 7-segment decoder for decimal numbers. It will help a lot!
• Review two's complement arithmetic and adders in the textbook.

Figure 1: Top-level view of the CALCULATOR circuit.

Design Specification

Restrictions

1. The top level module may be in schematic or Verilog.
   
2. Sub modules may be in schematic or Verilog.
3. You may use any Verilog constructs you learned thru  lab  3.
4. You can use the conditional ? operator. Look in the Verilog combinational reference or slides for details. It is a very powerful way to implement an N-bit, 2 to 1 multiplexer.
5. You CANNOT  use the "+" or "-" Verilog operator. This will greatly simply the design.
   
6. You may only use one n-bit ripple carry adder!! This will be strictly enforced. You can use the schematic editor version implemented in lab 2 or write it one in Verilog. Of course, you cannot use the + or - Verilog operator.
   
7. Your design should use combinational blocks that implement such functions as: ones complement, sign extension, MUXs and data path control.
8. The inputs A and B must be expressed as buses, ie A[3..0] and B[3..0]. See the accompanying guide on using buses for schematic entry.
   

Design Notes and Hints

• This problem is best approached by analyzing the common features among the various data operations (addition, subtraction, and absolute value) and designing an efficient multi-function datapath unit that can perform each of those operations in response to the applied opcodes. The core of the datapath must be an adder with appropriately-controlled multiplexers on its inputs in order to do addition, subtraction and absulute value. You will also need to design a "decoder" to display the two's complement result on the 7-segment LEDs.
• Big hint: You will want your adder to be 5-bits wide and you will want to sign-extend the 4-bit inputs to your 5-bit adder.
• The following module is a equivalent to a 4 bit, 2 to 1 multiplexer.

• This circuit can be designed flat by either drawing a single gate-level schematic. You'll be a lot more productive, though, if you use hierarchy to make your design modular; hierarchy can help you speed up both design entry and design verification. Components that you create are referred to as macros and are kept in a separate user library bearing your projects name. You should also consider using a fair bit of Verilog. It will make much of this design a lot easier to get right.
• The adder from lab 2 can be easily adapted to perform both addition and subtraction of two's complement numbers. See your textbook or course notes.
• Consider using buses to implement your data paths. Buses are a collection of nets represented in the schematic editor as a single thick line. For example, bus[7:0] representation the collection of nets bus7, bus6....bus0.You can simplify your connection between modules using buses. Where you may have to draw 8 wires between modules, you would only have to draw one 8 wire bus. There is also an example posted with this lab assignment. 
• The PreLab starting point solution illustrates the functional components and connections to implement much of the calculator functionality. It is incomplete! You will have to add more functionality to complete solution.
• The functional components illustrated in the PreLab starting point, may be implemented as schematic components that are connected in a top level schematic or they may be combined within Verilog modules. For example, the Sign Extension, Ones Complement and Mux may be combined into one Verilog module.

Deliverables

Demonstrate the operation of your final calculator design to the lab GSI. Be sure that the following cases work before demonstrating.

 1 + (-7) = -6
 0 - 7 = -7
 -1 + 1 = 0
 7 - (-8) = 15
 -8 + (- 8) = -16
 |7| = 7
 |-8| = 8
 

1. Provide schematic and/or verilog  design files depending on your implementation.(10 points)
   
2. Provide a functional simulation of your final calculator design for the following scenarios listed below.. The output must be provided directly from the adder, bypassing the 7 segment encoder. Add extra ports to your design to accomplish this. Notice writing all the test cases will be quite tedious with 16 cases per simulation! It is possible to use the for loop operator to generate the 16 test cases. In addition, using bus notation to make your port connections will greatly simplify the connection between the test cases and design module. An example test bench and simulation output for the first simulation case is provided. You must express the input arguments and sum output as a signed decimal number. To do this, in the waveform window, select the bused signals such as A_s, right click, select radix and then decimal.  (10 points each)
1.  5+(all possible values)
2.  abs(all possible values) (on B)
3.  4-(all possible values)

Appendix A: Using ?: to display values to the 7-segment display

assign bob=(mary==1'b1) ? 2'b01 : 2'b10;

if(mary==1'b1)
 bob=2'b01;
else
 bob=2'b10;

Consider the following coding example (parameter is a way to declare a constant).

module display(letter,seven);
 input [1:0] letter;
 output [6:0] seven;
 parameter F=7'b1000111;
 parameter S=7'b1011011;
 parameter r=7'b0000101;
 parameter L=7'b0001110;
 

 assign seven= (letter==2'b00 ? F:
 (letter==2'b01 ? S:
 (letter==2'b10 ? r:
 L)));
endmodule

Important: Quartus appears to occasionally be very sensitive to a lack of spaces around the ? operator.