- Overview
Taking a state-transition
diagram and converting it into
a state
machine is a mechanical process
which can be done quite well by a
computer. In this lab you will implement three versions of the same
state
machine, a 2-bit counter often used as a branch
predictor.
(You don't need to know anything about branch predictors to do this
lab!)
The first version will be a
schematic version where you figure out
all of
the gates needed by hand. The second version will be the same solution,
but
in Verilog this time. The third version will be another Verilog
solution,
but this time you will specify the state transition diagram and the
tools
will do the work of doing the gate layout.
- Preparation
- You will need to read the
sequential logic reference available
on the class website.
- You should understand what
a state machine and state diagram
are.
- Design
Specification
In this lab you are to design a device commonly used in modern
computers, a
"2-bit up/down saturating counter with enable" Such a counter is
defined as
follows:
- A two-bit counter uses two
bits to represent an unsigned
number. It is capable of counting from 0-3.
- An up/down counter is
capable of counting up (incrementing) or
down (decrementing).
- A saturating counter will
stay at its current value if asked to
increment or decrement out of its range. For example, in this case that
means if the counter is asked to count up past 3 it will stay at 3. If
it is asked to count down past 0, it will stay at 0.
- A counter with enable can
be told to stop counting.
Our device has three 1-bit inputs: "Reset", "Enable" and "Up/Down" and
two
1-bit outputs "Taken" and "Strong". When enable is 1, the counter is to
increment if "Up/Down" is 1 and decrement if "Up/Down" is 0. When
enable is
0, the counter should maintain its current value. When reset is 1 the
counter should go to 0 no matter what the other inputs might be. All of
the
the above should happen on each rising edge of the clock.
The output "Taken" should be
a 1 if the counter value is equal to
2 or 3, otherwise it should be 0. The output "Strong" should be a 1 if
the counter value is equal to 0 or 3, otherwise it should be 0.
Mapping
inputs and outputs
- "Clock" should be mapped
to Key0, such that pressing Key0
causes a rising edge.
- "Reset" should be mapped
to the leftmost dipswitch.
- "Up/Down" should be mapped
to dipswitch 0.
- "Enable" should be mapped
to dipswitch 1.
- "Taken" and "Strong"
should be mapped to Red LEDs 0 and 1
respectively.
Doing
it three times
You are to create three separate version of the design.
- Schematic
version: You are to use D
flip-flops (found
under primitives →
storage → dff) to
implement the
"state"
part of your device. The next state and output logic are to be done
using standard gates. Use the "CLRN" input of the flip-flop to
implement your reset logic (notice it is active low!). The
reset
will be asynchronous and while that is different than what you will do
in the other two versions, it is what is provided by the tools.
(In
general, you shouldn't use an asynchronous reset and in the pre-lab we
will ask you to build one with a synchronous reset.)
- Verilog
version I: You are to use an always
@(posedge clock) block to
implement your flip-flops. The next
state and output logic are to be done using assign statements (and only
using |, &, and ~). Reset should be done in the always block
(not
in the combinational logic).
- Verilog
version II: You are to use the
same always
@(posedge clock) block as
before for the flip-flops. But this time
you are to design your state machine as the example in the sequential
logic tutorial indicates. Again, reset is done in the sequential logic
portion.
You may NOT use an adder or
addition to solve this problem (but
see the post-lab).
- Design
Notes and Hints
- Doing the pre-lab before
implementing the first two parts will
help.
- Deliverables
Pre-Lab (35 Points)
- Provide a state-diagram
for this problem. Show what encodings
you will use for each state. Don't include reset. (10
points)
- Provide logic equations
for the outputs of your next-state
block
in sum-of-products form. Again, don't include reset. (15
points)
- Provide logic equations
for the outputs of your output block
in sum-of-producs form. (10
points)
Demonstrate
the "Verilog version I"
counter.