EECS 270: Sequential Lab 1

Introduction to State Machines and State

See the lab schedule for due dates.
Value: 100 points
v5/6/13

  1. Overview
  2. Taking a state-transition diagram and converting it into a state machine is a mechanical process which can be done quite well by a computer. In this lab you will implement three versions of the same state machine, a 2-bit counter often used as a branch predictor. (You don't need to know anything about branch predictors to do this lab!)

    The first version will be a schematic version where you figure out all of the gates needed by hand. The second version will be the same solution, but in Verilog this time. The third version will be another Verilog solution, but this time you will specify the state transition diagram and the tools will do the work of doing the gate layout.

  3. Preparation
  4. Design Specification
  5. In this lab you are to design a device commonly used in modern computers, a "2-bit up/down saturating counter with enable" Such a counter is defined as follows: Our device has three 1-bit inputs: "Reset", "Enable" and "Up/Down" and two 1-bit outputs "Taken" and "Strong". When enable is 1, the counter is to increment if "Up/Down" is 1 and decrement if "Up/Down" is 0. When enable is 0, the counter should maintain its current value. When reset is 1 the counter should go to 0 no matter what the other inputs might be. All of the the above should happen on each rising edge of the clock.

    The output "Taken" should be a 1 if the counter value is equal to 2 or 3, otherwise it should be 0. The output "Strong" should be a 1 if the counter value is equal to 0 or 3, otherwise it should be 0.

    Mapping inputs and outputs

    Doing it three times
    You are to create three separate version of the design.

    You may NOT use an adder or addition to solve this problem (but see the post-lab).

  6. Design Notes and Hints
  7. Deliverables
  8. Pre-Lab (35 Points)
    1. Provide a state-diagram for this problem. Show what encodings you will use for each state. Don't include reset. (10 points)
    2. Provide logic equations for the outputs of your next-state block in sum-of-products form. Again, don't include reset. (15 points)
    3. Provide logic equations for the outputs of your output block in sum-of-producs form. (10 points)

    In-lab (25 points)

Demonstrate the "Verilog version I" counter.

    Post-Lab (40 Points)

    1. Provide schematic and Verilog designs of the 3 versions. (no qsf files)  (10 points)
    2. Provide answers to the following questons.
      1. Why do you think we didn't include reset in questions 1 and 2 of the pre-lab? It might also have been reasonable to leave out enable. Why? (hint: look at the different D flip-flops available for the schematic capture.) (5 points)
      2. Your "Verilog version II" code was likely longer than the version I code. Why don't we generally design state machines the way we did in version I? Will the version I way generally be shorter? (5 points)
      3. Say we wanted to change the design so that the counter wraps around rather than saturates. Which of your three designs would be easiest to change? Explain why. (5 points)
      4. How many "logic elements" where used by each of your designs ((examine the Flow summary report that comes up after you compile). (5 points)
    3. Provide another version of your next state logic for "Verilog version II", but this time using + and - operators. Assume the state assignment is the obvious two-bit assignment (ZERO=2'b00, ONE=2'b01, etc.). It does not have to compile.  (10 points).