Majority Voter Test Bench (truth table style procedure)
This method uses a Verilog initial procedure and delays to provide all
the possible input combinations.
// means a
comment follows
`timescale 1 ns/1 ns //time scale for the test bench
module
tutorialtb(); // the test bench module
reg
A_s, B_s, C_s; //define input ports
wire M_s;
//define output port
//
the following creates (instantiates) your majority voter logic
(tutorial), creates an intance of it (t1)
//and passes the inputs from the test procedure below
tutorial
t1(.A(A_s),
.B(B_s),.C( C_s),.M(M_s));
//what
follows is the test procedure
initial
begin
//test
all possible
input conditions
//#10 means wait 10 time scale units (defined to be ns above)
A_s <= 0; B_s <= 0; C_s
<=0; #10;
A_s
<= 1; B_s
<= 0; C_s <=0; #10;
A_s
<= 0; B_s
<= 1; C_s <=0; #10;
A_s
<= 1; B_s
<= 1; C_s <=0; #10;
A_s
<= 0; B_s
<= 0; C_s <=1; #10;
A_s
<= 1; B_s
<= 0; C_s <=1; #10;
A_s
<= 0; B_s
<= 1; C_s <=1; #10;
A_s
<= 1; B_s
<= 1; C_s <=1; #10;
end
endmodule