Majority Voter Test Bench (counter stimulus method)
This is another way to provide all the input combinations to test the majority voter.
This method uses a Verilog always procedure to create 3 waveforms delay in time to provide all the input conditions. The procedure will continue as long as the simulation is run.


`timescale 1 ns/1 ns

module vmtbclk();

reg Clka_s, Clkb_s, Clkc_s;
wire M_s;

mv mv2(.A(Clka_s),.B(Clkb_s),.C(Clkc_s),.M(M_s));

//the following test procedure create 3 waveforms
//1 with a 20n period, 10ns high, 10ns low
//1 with a 40n period, 20ns high, 20ns low
//1 with a 80n period, 40ns high, 40ns low
always begin
  Clka_s <=1;    //set output to 1
  #10             //wait 10 ns
  Clka_s <=0;     //set output to 0
  #10                //wait 10ns
  Clkb_s <=1;    //etc
  #20
  Clkb_s <=0;
  #20
  Clk_s <= 1;
  #40
  Clk_s <= 0;
end