This assignment is worth about 1% of your grade in the class and is graded out of 30 points. Remember you may drop one individual homework assignment.

1. 6.11 (part a only) [2]
2. 6.17. Clearly show your work. You should use the algorithm we did in class. It is the same as the one in the text, the text's version of it is a bit less formal. [5]
3. Using an up-counter (with reset), a flip-flop, and basic gates, build a device that divides the frequency of a clock by 20 and has a 25% duty cycle (high for 25% of the time). The output must be glitch free. [4]
4. Design a 3-input AND gate using static-CMOS rules. [1]
5. Design a non-inverting tristate buffer using static-CMOS rules (well, at least that the PUN must be PMOS and the PDN must be NMOS). [3]
6. 6.22 [3]
7. 6.23 [3]
8. Do the following:
   1. Design a state transition diagram for a clocked state machine with one input, X, and one Moore-type output Z. Z should be a 1 iff the last 4 values of X were "1010". Use as few states as possible. [3]
   2. Design a state transition diagram for a clocked state machine with one input, X, and one Mealy-type output Z. Z should be a 1 iff the last 4 values of X were "1010". Use as few states as possible. [3]
   3. Generate a timing diagram for the two above designs. Show Clock, X and Z for both. Assume X is changing on the falling edge of the clock. Assume negligible delay.Use the input 1010100. [3]