Group Assignment 2 -- EECS 270, Spring '23
Due Wednesday, May 17th @9pm, 5% off if turned in by 11pm
This is a group assignment, all of the work should be that of only your
group members. Assignments that are unstapled, lack a cover sheet, or are
difficult to read will lose at least 50% of the possible points and we may
not grade them at all.
It is expected that each group member contributed to the assignment;
non-contributing members should not have their name on this document. This
assignment is worth about 1% of your grade in the class and is graded out of 30
points. Remember you may drop one group assignment.
- Using standard gates as well as full-adders, design a 4-bit ripple-carry adder with
overflow detection. The device should take 2 4-bit inputs "X[3:0]" and
"Y[3:0]" and generate the following outputs:
- The result of the addition, "S[3:0]"
- Iff overflow occurred for an unsigned addition, "UO" should be a 1.
- Iff overflow occurred for an 2's complement addition, "TO" should be a 1.
UO and TO should be 1 iff the addition overflows the associated
representation (the 4-bit adder should be easy, the overflow is the hard
part here). [10]
- Say you have one input, X as well as a single output Y. Y
should go high iff the last four values of X were either "1001", "0111" or "110".
Design a state-transition diagram for this device using as few states as you
can. Your initial state should assume that all bits on X up to this time
have been "0" (so we start with an infinite number of zeros having occurred).
X. [15, 9 points are for a correct answer, 6 for using the smallest number of states with a correct answer]
- Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [5]