Name: _______________________________ unique name: ________________

Name: _______________________________ unique name: ________________

You are to turn in this sheet as a cover page for your assignment. This is a group assignment, all of the work should be that of only your group members. Assignments that are unstapled, lack a cover sheet, or are difficult to read will lose at least 50% of the possible points and we may not grade them at all.

It is expected that each group member contributed to the assignment; non-contributing members should not have their name on this document. This assignment is worth about 1% of your grade in the class and is graded out of 30 points.

1. Consider a set of gates which generate one output from four inputs. The inputs are named A3, A2, A1, and A0 and the output is named primeZ. The inputs are treated as a 4-digit unsigned binary number with A3 being the most significant bit. So A3=1, A2=1, A1=1, A0=0 is treated as 1110 base 2 (1110₂) which is 14 in base 10 (14₁₀). PrimeZ should be a one iff (if and only if) the input is a prime number or if it is zero. (Recall that zero and one are not prime numbers.)

   (Note on syntax: Writing A3=1, A2=1, A1=0, A0=1 is a bit combersume. Traditionaly we'd write A[3:0]=1101.)

   Examples:

   • if A[3:0]=1010 then primeZ should be a 0 (10₁₀ is neither a prime number nor zero).
   • if A[3:0]=1101 then primeZ should be a 1 (13₁₀ is a prime number).
   • if A[3:0]=0000 then primeZ should be a 1 (0 isn't a prime, but it is zero).

   Your task is to draw a logic circuit using only two-input AND, OR, NAND, NOR XOR and XNOR gates as well as one-input NOT gates. Further, you are not allowed to have any gate or input have a fan-out greater than 4. (This means that no gate or input is allowed to act as the input for more than 4 gates.) Your job is to minimize the worst case delay through the circuit using the assumptions on delay found below.

   You are to assume that NOT gates have a delay of 2, NAND and NOR have a delay of 3, AND and OR have a delay of 5, and XOR and XNOR have a delay of 6.

   Grading for this problem will be based upon correctness and (assuming it is correct) worst case delay. You can also lose points for sloppy or otherwise flawed solutions (like calculating the worst-case delay incorrectly). Scoring:

   • Correct and a delay greater than or equal to 30 -- 15 points
   • Correct and a delay from 24-29 -- 20 points
   • Correct and a delay from 20-23 -- 25 points
   • Correct and a delay from 15-19 -- 28 points
   • Correct and a delay less than 15 -- 30 points
   (For the record, the instructors have a solution that has a worst-case delay of 22. We aren't really sure what the best you can do is. It may be that 25 points is the most anyone will earn on this but we strongly suspect there is a 14 solution.)

   Further the best team (lowest delay) will get 6 point bonus. If there is a tie the group with the fewest total gates will win. If that's a tie they will split the 6 points amoung the tieing teams.

   Your group is to turn in:

   • A neat circuit diagram with the worst-case path highlighted and what you believe to be your worst-case delay.

   Be sure you double-check that your diagram produces the right output before you turn it in. It's easy to mess it up. Don't forget to attach the coversheet.