module counter(clock, reset, count);
    input clock, reset;
    output [3:0] count;
    
    reg [3:0] next_count,count;

    always@*
    begin
        if(count<15)
            next_count=count+4'd1;
        else
            next_count=count;
    end

    always@(posedge clock)
    begin
        if(reset)
           count<=4'd0;
        else
           count<=next_count;
    end
endmodule