- See 2.10, page 85 of Vahid for a discussion on propagation delay.
- See 4.3 of Vahid for half, full and binary ripple carry adder operation. We will use the binary carry adder to demonstrate the effects of propagation delay on adder operation.
Figure 1: 5-input XOR
Figure 2: 4-bit adder
You will be creating two different projects, one with the five-input XOR, and one with the ripple-carry adder. You will then examine the propagation delay of the circuit using both a simple abstract model and then using the Quartus tools to provide a "real" model of the FPGA delay. For the 5-input XOR gate you are to use switches SW0-SW4 (in any order) as your inputs and LEDR[0] as the output.
For the adder SW[3:0] will be "A[3:0]" (in that order), SW[7:4] will B[3:0] (again in that order) and Cin will be KEY3 (recall that the KEY inputs are active low). Your outputs will have S[3:0] mapped to LEDR[3:0] and Cout mapped to LEDG[7].
Implementation details
The 5-input XOR gate should be straightforward to implement. The XOR gates
needed are found on the symbol tool under "primitives → logic". The
ripple-carry adder requires you to learn a few more things about the Quartus
tools, so we will step you through it.
Don't forget to save the project early and often!
Once you've finished copying the 5-input XOR design, you will need to do the following to get the 4-bit adder working:
- First, don't forget you want to to start a new project when doing the ripple-carry adder. That is, the adder and the 5-input XOR should be different projects (and ideally different directories).
- Once you've created a new project for the adder, the first thing you
should do is create a schematic as shown in Figure 3. Be sure to name
everything the same as we did (though don't worry about instance numbers).
Figure 3: Full-adder - Save the schematic as "full_adder".
- Now select "File → Create/Update → Create Symbol files for the current file". You should get a message telling you that it was successful.
- Now open a new schematic and name it whatever you chose as your top module. (That should be the default when you try to save it.)
- When you open the symbol tool, a new option appears "Project". See
Figure 4. Select "Project → full_adder" from the symbol tool menu and
place the full-adder in your schematic.
Figure 4: New option in the symbol tool. - This would be a good time to save!
- Now the full-adder symbol probably doesn't have the inputs and outputs in the same order as they are in Figure 2. So what you need to do right-click on the full_adder symbol and select "Edit Selected Symbol".
- You should find that by grabbing the wires with the mouse (not the text!) you can change the order of the signals. Make it match what you see in Figure 2 (Cin on the top right, then A then B. On the left you have S on the top then Cout.) Try to keep the spacing about the same as it was.
- Save the file (use the default name which should full_adder.bsf) then close the file ("File → Close").
- This would be a good time to save.
- Now back in the top-level file you will notice that the order of the adder's inputs and outputs haven't changed. Select the adder, right click on it, and then choose "Update symbol or block". That pops up a window asking what you want to update. In this case it doesn't matter which of the options you select (the default is fine).
- Now all you need to do is make your figure look like Figure 2. Be sure to name everything correctly!
You will now need to edit the .qsf file for both projects to properly set-up the switches. This should be very similar to what you did in lab 1.
- Again, don't forget to save often. Especially when playing with the schematic editor, the software will occasionally crash.
- When you want to run wires from one place to another, you can't generally just drag the wires from start to finish and expect it to look good. You will often need to draw the wire "part way" and then start it from there.
- The last pre-lab question is fairly hard, allow time for getting help as it may be needed.
- The timing simulation provides a fairly accurate measure of the actual
delays of a given design on our FPGA. Getting a timing simulation working
is a bit tricky. It is similar to a function simulation except:
- You should completely build the circuit (In the Compiler tool, press the "Start" button). This may take a while.
- In the simulation tool you need to select "Timing" not "Functional", and you don't need to generate a Functional Netlist.
- The timing simulation will likely provide some non-intuitive results. It is due to a combination of optimization by the compiler and how an FPGA works (it doesn't use individual gates). Your GSI will provide a brief explanation during the lab section when the in-lab is turned in.
- Pre-Lab (30 points)
- Hardcopy of schematic and the .qsf files for both circuits. (8 points)
- For the 5-input XOR, assume that each XOR gate has a delay of 5ns. Complete the supplied timing diagram. The entries "1", "2", and "3" are to be the intermediate nodes, where "1" is the output of the first XOR (has V and W as inputs) and "2" is the next XOR output, etc. Use a straight-edge to draw your lines. (8 points)
- If SW[7:0]=0x3C and KEY3 is not pressed, which LEDs do you expect to see lit? Recall that KEY3 is active low. What if SW[7:0]=0x77 and KEY3 was not pressed? (4 points)
- For the 4-bit adder again assume each full adder has a delay of 5ns. Show what would happen to the outputs (S[3:0] and Cout) over time if the inputs of A started at hex "4" and became hex "1" at time 20ns, while B stays at hex "7" and Cin stayed 0. Draw a timing diagram showing each of the five outputs as individual wires as well as showing the hex value output on S[3:0]. Your diagram should be neat (use a straight-edge or a drawing program). (10 points)
- In-Lab (15 points)
- Post-lab (30 points)
- Prepare your lab report as described in the EECS270 Laboratory Overview handout. Make sure you complete and include all parts of the report including the Cover Sheet and the Design Documentation section. (10 points)
- Provide a printout of a timing simulation of the 4-bit adder. Use the same inputs that you used in the hand drawing for the pre-lab. (10 points)
- Answer the following questions:
- If each full adder in the 4-bit adder had a propagation delay of 5ns, what would be the worst-case delay before the adder output the correct answer? (3 points)
- If each gate in the 4-bit adder had a propagation delay of 3ns, what would be the worst-case delay before the adder output the correct answer? (3 points)
- For your above answer provide an example case which produces that worst-case delay (hint: you will need to say what all the inputs start as and which input(s) are changing). (4 points)
Demonstrate that your two circuits work correctly on the board. Also, show
that you can perform a timing simulation of the 5-input XOR circuit.
You should keep all of the inputs held at zero and have the "V" input be a
clock with a 40ns period and a 50% duty cycle. On the screen you should
show the output from time 0 to about 100ns.