EECS 270: Lab 4

Overview

Preparation

• You will need to read the sequential logic tutorial available on the class website.
• You should understand what a state machine and state diagram are as well as how a flip-flop is implemented. Review Chapter 3 as needed.

Design Specification

• A two-bit counter uses two bits to represent an unsigned number. It is capable of counting from 0-3.
• An up/down counter is capable of counting up (incrementing) or down (decrementing).
• A saturating counter will stay at its current value if asked to increment or decrement out of its range. For example, in this case that means if the counter is asked to count up past 3 it will stay at 3. If it is asked to count down past 0, it will stay at 0.
• A counter with enable can be told to stop counting.

The output "Taken" should be a 1 if the counter value is equal to 2 or 3, otherwise it should be 0. The output "Strong" should be a 1 if the counter value is equal to 0 or 3, otherwise it should be 0.

Mapping inputs and outputs

• "Clock" should be mapped to Key3, such that pressing Key3 causes a rising edge.
• "Reset" should be mapped to the leftmost dipswitch.
• "Up/Down" should be mapped to dipswitch 0.
• "Enable" should be mapped to dipswitch 1.
• "Taken" and "Strong" should be mapped to LEDs 0 and 1 respectively.

Doing it three times
You are to create three separate version of the design.

• Schematic version: You are to use D flip-flops (found under primitives → storage → dff) to implement the "state" part of your device. The next state and output logic are to be done using standard gates. Use the "CLRN" input of the flip-flop to implement your reset logic (notice it is active low!). The reset will be asynchronous and while that is different than what you will do in the other two versions, it is what is provided by the tools. (In general, you shouldn't use an asynchronous reset and in the pre-lab we will ask you to build one with a synchronous reset.)

• Verilog version I: You are to use an always @(posedge clock) block to implement your flip-flops. The next state and output logic are to be done using assign statements (and only using |, &, and ~). Reset should be done in the always block (not in the combinational logic).

• Verilog version II: You are to use the same always @(posedge clock) block as before for the flip-flops. But this time you are to design your state machine as the example in the sequential logic tutorial indicates. Again, reset is done in the sequential logic portion.

You may NOT use an adder or addition to solve this problem (but see the post-lab).

Design Notes and Hints

• Doing the pre-lab before implementing the first two parts will help.

Deliverables

1. Draw a state-diagram for this problem. Show what encodings you will use for each state. Don't include reset. (10 points)
2. Write logic equations for the outputs of your next-state block in sum-of-products form. Again, don't include reset. (15 points)
3. Write logic equations for the outputs of your output block in sum-of-products form. (5 points)

In-lab (25 points)
Demonstrate the "Verilog version I" state machine.

Post-Lab (45 Points)

1. Turn in printouts of your three designs. (10 points)
2. Answer the following questions:
   1. Why do you think we didn't include reset in questions 1 and 2 of the pre-lab? It might also have been reasonable to leave out enable. Why? (hint: look at the different D flip-flops available for the schematic capture.) (5 points)
   2. Your "Verilog version II" code was likely longer than the version I code. Why don't we generally design state machines the way we did in version I? Will the version I way generally be shorter? (5 points)
   3. Say we wanted to change the design so that the counter wraps around rather than saturates. Which of your three designs would be easiest to change? Explain why. (5 points)
3. Rewrite the next state logic for "Verilog version II", but this time using + and - operators. Assume the state assignment is the obvious two-bit assignment (ZERO=2'b00, ONE=2'b01, etc.). (15 points).
4. How many "logic elements" where used by each of your designs (examine the Flow summary report that comes up after you compile). (5 points)