EECS 270: Lab 5

Overview

Preparation

• Read the example found at the end of this lab about how to use MUXes to design a 7-segment decoder for decimal numbers. It will help a lot!
• Review two's complement arithmetic and adders in the textbook.

Figure 1: Top-level view of the CALCULATOR circuit.

Design Specification

Verilog and schematic restrictions
Your top-level module must be a schematic. You are welcome to use Verilog as much as you want, but the top-level schematic will hopefully aid you in visualizing your solution.

In this lab you are restricted to the same set of Verilog you used in lab 3 with two exceptions. First, you may now use the "?:" operator, which acts like a MUX (see Appendix A of this document for details.) You may also use the "==" operator to check for equality. You specifically may not use operations like '+' and '-'.

On the schematic side you may freely use gates, MUXes, encoders and decoders.

In all cases, you are to use only one adder.

Design Notes and Hints

• This problem is best approached by analyzing the common features among the various data operations (addition, subtraction, and absolute value) and designing an efficient multi-function datapath unit that can perform each of those operations in response to the applied opcodes. The core of the datapath must be an adder with appropriately-controlled multiplexers on its inputs in order to do addition, subtraction and absulute value. You will also need to design a "decoder" to display the two's complement result on the 7-segment LEDs.

• Big hint: You will want your adder to be 5-bits wide and you will want to sign-extend the 4-bit inputs to your 5-bit adder.

• This circuit can be designed flat by either drawing a single gate-level schematic. You'll be a lot more productive, though, if you use hierarchy to make your design modular; hierarchy can help you speed up both design entry and design verification. Components that you create are referred to as macros and are kept in a separate user library bearing your projects name. You should also consider using a fair bit of Verilog. It will make much of this design a lot easier to get right.

• The adder from lab 2 can be easily adapted to perform both addition and subtraction of two's complement numbers. See your textbook or course notes.

• Consider using buses to implement your data paths. Buses are a collection of nets represented in the schematic editor as a single thick line. For example, bus[7:0] representation the collection of nets bus7, bus6....bus0.You can simplify your connection between modules using buses. Where you may have to draw 8 wires between modules, you would only have to draw one 8 wire bus. Your lab instructor will spend a bit of time discussing how to use buses, though you can also use the help features of Quartus.

Deliverables

1. Answer the following questions:
   1. What is the range of positive and negative input values? Give your answer in decimal. (5 points)
   2. What is the range of possible positive and negative output values given the above input values? Give your answer in decimal. (5 points)
   3. Using both 4-bit and 5-bit two's complement representation, express the numbers 3, -3, 7 and -7. (5 points)
2. Design a ripple carry adder macro using the full 1 bit adder from lab 2 to perform the following operations in a functional simulation:
   1. 3+4 with Cin=1
   2. 3+(-4) with Cin=0
   3. -8+-8 with Cin=0
   Turn a single printout showing these three operations in functional simulation. Explain any issues with the answers gotten. Clearly label which part of the simulation is doing which operation (a, b, c). (20 points)

3. For this problem, say you have an adder with inputs labeled X[4:0], Y[4:0] and Cin, with outputs R[4:0] and Cout. Assume the inputs to your calculator are labeled A[3:0] and B[3:0] and that your output is called H[4:0]. H[4:0] is the 2's complement binary representation of the answer, not the encoding sent to the 7-segment displays. You may use conditionals to express your answer (so "if A[2]==1 then..." is okay). (20 points)
   1. If you are to compute A+B, what should be passed to X, Y and Cin in the general case? In addition provide specific (binary) values for the case when A=-3 and B=3.
   2. If you are to compute A-B, what should be passed to X, Y and Cin in the general case? In addition provide specific (binary) values for the case when A=-3 and B=3.
   3. If you are to compute |A|, what should be passed to X, Y and Cin in the general case? In addition provide specific (binary) values for the case when A=-3 and B=3.
   4. If you are to compute |B|, what should be passed to X, Y and Cin in the general case? In addition provide specific (binary) values for the case when A=-3 and B=3.

In-lab (55 points)
Demonstrate the operation of your final calculator design to the lab GSI. Be sure that the following cases work before demonstrating.

 1 + (-7)   = -6
 0 - 7      = -7
 -1 + 1     = 0
 7 - (-8)   = 15
 -8 + (- 8) = -16
 |7|        = 7
 |-8|       = 8
 

1. Simulate your calculator design for the following scenarios. You are to:
   • Provide hardcopy of each simulation on its own print-out.
   • Include A, B, C inputs and express each as buses in hex.
   • Use the binary outputs, NOT the 7 segment outputs. Express as buses in hex.
   • Clearly label each time period was corresponding to a given scenario (a, b, etc.)
   • Clearly label each printout by scenario name.
   • Use the "Count value" icon () in the simulator to generate all possible values.
   • Scenarios: (10 points each)
     1. 5+(all possible values)
     2. abs(all possible values) (on B)
     3. 4-(all possible values)
2. Submit a top-level design, all Macro contents, and qsf files (15 points)

Appendix A: Using ?: to display values to the 7-segment display

assign bob=(mary==1'b1) ? 2'b01 : 2'b10);

if(mary==1'b1)
  bob=2'b01;
else
  bob=2'b10;

Consider the following coding example (parameter is a way to declare a constant).

module display(letter,seven);
  input [1:0] letter;
  output [6:0] seven;
  parameter F=7'b1000111;
  parameter S=7'b1011011;
  parameter r=7'b0000101;
  parameter L=7'b0001110;
 

  assign seven= (letter==2'b00 ? F:
                (letter==2'b01 ? S:
                (letter==2'b10 ? r:
                 L)));
endmodule

Important: Quartus appears to occasionally be very sensitive to a lack of spaces around the ? operator.